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| author | Yanzhang Wang <yanzhang.wang@intel.com> | 2023-12-08 10:32:59 +0800 |
|---|---|---|
| committer | Yanzhang Wang <yanzhang.wang@intel.com> | 2023-12-08 11:05:14 +0800 |
| commit | 72a1fc005c08605c94061d01022b5454ea6e3062 (patch) | |
| tree | d2092a1f4061bd3d1e2ba8191d1b5ff1870ea253 | |
| parent | fcc49c7f4a19f6c41383894ef55e0488751ae875 (diff) | |
| download | riscv-gnu-toolchain-72a1fc005c08605c94061d01022b5454ea6e3062.zip riscv-gnu-toolchain-72a1fc005c08605c94061d01022b5454ea6e3062.tar.gz riscv-gnu-toolchain-72a1fc005c08605c94061d01022b5454ea6e3062.tar.bz2 | |
Add misaligned memory access for spike.
The spec does not forbid the misaligned memory access. And the gcc
will generate vector load/store to access misaligned memory by
default.
Currently the QEMU supports this feature, so to support in spike
is also make sense.
Reference test case: gcc/gcc/testsuite/gcc.dg/vect/vect-align-1.c
| -rwxr-xr-x | scripts/wrapper/spike/riscv64-unknown-linux-gnu-run | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/scripts/wrapper/spike/riscv64-unknown-linux-gnu-run b/scripts/wrapper/spike/riscv64-unknown-linux-gnu-run index fb569f1..29f9bf3 100755 --- a/scripts/wrapper/spike/riscv64-unknown-linux-gnu-run +++ b/scripts/wrapper/spike/riscv64-unknown-linux-gnu-run @@ -6,7 +6,8 @@ varch="$(march-to-cpu-opt --elf-file-path $1 --print-spike-varch)" isa_option="--isa=${isa}" varch_option="" +memory_option="--misaligned" [[ ! -z ${varch} ]] && varch_option="--varch=${varch}" -spike ${isa_option} ${varch_option} ${PK_PATH}/pk${xlen} "$@" +spike ${memory_option} ${isa_option} ${varch_option} ${PK_PATH}/pk${xlen} "$@" |