1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
|
// See LICENSE for license details.
#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
#include "../p/riscv_test.h"
#undef EXTRA_INIT_TIMER
#define EXTRA_INIT_TIMER \
ENABLE_TIMER_INTERRUPT; \
j 6f; \
XCPT_HANDLER; \
6:
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
#undef EXTRA_DATA
#define EXTRA_DATA \
.align 3; \
regspill: \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
evac: \
.skip 32768; \
//-----------------------------------------------------------------------
// Misc
//-----------------------------------------------------------------------
#define ENABLE_TIMER_INTERRUPT \
csrw clear_ipi,x0; \
csrr a0,status; \
li a1,SR_IM; \
or a0,a0,a1; \
csrw status,a0; \
la a0,_handler; \
csrw evec,a0; \
csrw count,x0; \
addi a0,x0,100; \
csrw compare,a0; \
csrs status,SR_EI; \
#define XCPT_HANDLER \
_handler: \
csrw sup0,a0; \
csrw sup1,a1; \
csrr a0,cause; \
li a1,CAUSE_SYSCALL; \
bne a0,a1,_cont; \
li a1,1; \
bne x27,a1,_fail; \
_pass: \
fence; \
csrw tohost, 1; \
1: j 1b; \
_fail: \
fence; \
beqz TESTNUM, 1f; \
sll TESTNUM, TESTNUM, 1; \
or TESTNUM, TESTNUM, 1; \
csrw tohost, TESTNUM; \
1: j 1b; \
_cont: \
csrr a0,impl; \
li a1,IMPL_ROCKET; \
beq a0,a1,_rocket_handler; \
vxcptcause x0; \
la a0,evac; \
vxcptsave a0; \
vxcptrestore a0; \
j _exit; \
\
_rocket_handler: \
la a0,regspill; \
sd a2,0(a0); \
sd a3,8(a0); \
sd a4,16(a0); \
sd a5,24(a0); \
sd s0,32(a0); \
sd s1,40(a0); \
vgetcfg s0; \
vgetvl s1; \
la a0,evac; \
vxcptevac a0; \
vsetcfg s0; \
vsetvl s1,s1; \
vxcpthold; \
li a5,0; \
_handler_loop: \
ld a1,0(a0); \
addi a0,a0,8; \
blt a1,x0,_done; \
srli a2,a1,32; \
andi a2,a2,0x1; \
beq a2,x0,_vcnt; \
_vcmd: \
beq a5,x0,_vcmd_skip; \
venqcmd a4,a3; \
_vcmd_skip: \
li a5,1; \
move a4,a1; \
srli a3,a4,36; \
andi a3,a3,0x1; \
_vimm1: \
srli a2,a4,35; \
andi a2,a2,0x1; \
beq a2,x0,_vimm2; \
ld a1,0(a0); \
addi a0,a0,8; \
venqimm1 a1,a3; \
_vimm2: \
srli a2,a4,34; \
andi a2,a2,0x1; \
beq a2,x0,_end; \
ld a1,0(a0); \
addi a0,a0,8; \
venqimm2 a1,a3; \
j _end; \
_vcnt: \
ld a2,0(a0); \
srli a2,a2,31; \
andi a2,a2,0x2; \
or a3,a3,a2; \
venqcnt a1,a3; \
_end: \
j _handler_loop; \
_done: \
beq a5,x0,_done_skip; \
venqcmd a4,a3; \
_done_skip: \
la a0,regspill; \
ld a2,0(a0); \
ld a3,8(a0); \
ld a4,16(a0); \
ld a5,24(a0); \
ld s0,32(a0); \
ld s1,40(a0); \
\
_exit: \
csrs status,SR_PEI; \
csrc status,SR_PS; \
csrr a0,count; \
addi a0,a0,100; \
csrw compare,a0; \
csrr a0,sup0; \
csrr a1,sup1; \
sret; \
#undef RVTEST_PASS
#define RVTEST_PASS \
li x27, 1; \
scall; \
#undef RVTEST_FAIL
#define RVTEST_FAIL \
li x27,2; \
scall; \
#endif
|
