Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2016-03-14 | Support RV32 virtual memory testspriv-1.9 | Andrew Waterman | 4 | -13/+129 | |
2016-03-02 | WIP on priv spec v1.9 | Andrew Waterman | 2 | -7/+43 | |
2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 6 | -178/+147 | |
2015-11-06 | Add custom opcodes back to encoding.h | Andrew Waterman | 1 | -76/+172 | |
2015-09-28 | make sure TESTNUM is initialized | Howard Mao | 1 | -0/+1 | |
2015-09-20 | Remove Hwacha v3 support | Andrew Waterman | 7 | -878/+533 | |
2015-07-17 | don't pass fpu/vector tests when fpu/vector not present | Yunsup Lee | 1 | -10/+1 | |
2015-07-06 | Coherence torture test for VM tests | Andrew Waterman | 1 | -1/+24 | |
VM tests only support one core, so have the other cores hammer on the memory system to attempt to catch simple coherence regressions. | |||||
2015-07-05 | New M-mode timers; don't use sscratch in M-mode | Andrew Waterman | 2 | -50/+78 | |
2015-06-23 | Avoid "csrw stvec" if stvec_handler doesn't exist. | Christopher Celio | 1 | -1/+2 | |
2015-05-19 | Improve coverage of VM tests | Andrew Waterman | 4 | -46/+89 | |
The supervisor code now runs in supervisor mode with negative virtual addresses. This further stresses VM and tests some RV64 corner cases. | |||||
2015-05-11 | Initialize FCSR | Andrew Waterman | 1 | -1/+1 | |
2015-05-11 | Fix VM, MIP encoding | Andrew Waterman | 1 | -6/+6 | |
2015-05-09 | Update to privileged architecture version 1.7 | Andrew Waterman | 9 | -320/+193 | |
2015-04-03 | Rename VM_SV43 to VM_SV39 | Andrew Waterman | 2 | -5/+7 | |
2015-04-03 | Don't assume initial values of mstatus.ua/sa | Andrew Waterman | 1 | -5/+15 | |
2015-03-30 | Don't rely on mstatus.fs to test FPU presence | Andrew Waterman | 1 | -9/+11 | |
2015-03-27 | New virtual memory implementation (Sv39) | Andrew Waterman | 3 | -435/+519 | |
2015-03-25 | add mtvec_handler to machine traps from user land | Yunsup Lee | 1 | -11/+22 | |
2015-03-24 | Don't assume PRV1/2 and IE1/2 are reset | Andrew Waterman | 1 | -2/+4 | |
2015-03-17 | relay hwacha cause/aux to scause/sbadaddr | Yunsup Lee | 1 | -1/+11 | |
2015-03-17 | change hwacha cause to follow risc-v cause | Yunsup Lee | 1 | -12/+14 | |
2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 5 | -36/+25 | |
2015-03-16 | clean up pt and vector environments | Yunsup Lee | 6 | -175/+166 | |
2015-03-14 | Check referenced/dirty bits | Andrew Waterman | 1 | -1/+7 | |
2015-03-12 | Use hcall instead of mcall | Andrew Waterman | 2 | -12/+17 | |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 7 | -300/+381 | |
2015-03-12 | Fix include guard | Albert Ou | 1 | -1/+1 | |
2015-01-09 | Add LICENSE | Andrew Waterman | 7 | -0/+36 | |
2015-01-04 | Avoid deprecated "b" pseudo-op; use "j" instead | Andrew Waterman | 2 | -5/+5 | |
2014-11-25 | use new calling convention | Andrew Waterman | 2 | -23/+22 | |
2014-11-22 | Revert "Enable support for the four custom instructions" | Yunsup Lee | 1 | -72/+0 | |
This reverts commit 2397975ca52528ed0d8e4e35d58c3eca5b9e4112. Refactoring support for custom instructions. | |||||
2014-11-06 | Improve VM env debug messages | Andrew Waterman | 1 | -6/+6 | |
2014-10-24 | Merge pull request #1 from arunthomas/custom_inst | Yunsup Lee | 1 | -0/+72 | |
Enable support for the four custom instructions | |||||
2014-10-23 | Enable support for the four custom instructions | Arun Thomas | 1 | -0/+72 | |
* Update generated encoding.h (generated from riscv-opcodes) | |||||
2014-04-03 | Sync encoding.h with opcodes | Stephen Twigg | 1 | -43/+61 | |
2014-03-03 | need to modify status register *before* enabling interrupts | Yunsup Lee | 1 | -2/+2 | |
2014-03-02 | Renumber uarch CSRs into custom CSR space | Yunsup Lee | 1 | -16/+16 | |
2014-02-27 | enable interrupts *after* setting the evec register | Yunsup Lee | 1 | -1/+1 | |
2014-02-25 | make physical timer env work again | Yunsup Lee | 2 | -23/+47 | |
2014-02-06 | fix recursive interrupts, and more improvements to code | Yunsup Lee | 3 | -15/+29 | |
2014-02-06 | Improve trap entry code | Andrew Waterman | 3 | -35/+23 | |
2014-02-06 | Update CSRs | Andrew Waterman | 1 | -48/+48 | |
2014-02-06 | Update CSRs | Andrew Waterman | 1 | -13/+96 | |
2014-02-06 | fix vector exceptions on rocket | Yunsup Lee | 2 | -24/+15 | |
2014-01-31 | Support RV32S tests | Andrew Waterman | 1 | -0/+5 | |
2014-01-31 | Use TESTNUM instead of x28 directly | Andrew Waterman | 2 | -29/+19 | |
2014-01-20 | Update encoding.h to reflect JALR, RDCYCLE changes | Quan Nguyen | 1 | -24/+24 | |
2014-01-16 | Source test failure value from correct register | Andrew Waterman | 1 | -4/+4 | |
2014-01-13 | Assume pc-relative addressing | Andrew Waterman | 2 | -26/+26 | |