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-rw-r--r--p/riscv_test.h8
-rw-r--r--v/entry.S2
2 files changed, 10 insertions, 0 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h
index a8c50c7..7bf35cf 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -107,6 +107,13 @@
.align 2; \
1:
+#define INIT_RNMI \
+ la t0, 1f; \
+ csrw mtvec, t0; \
+ csrwi CSR_MNSTATUS, MNSTATUS_NMIE; \
+ .align 2; \
+1:
+
#define INIT_SATP \
la t0, 1f; \
csrw mtvec, t0; \
@@ -197,6 +204,7 @@ handle_exception: \
reset_vector: \
INIT_XREG; \
RISCV_MULTICORE_DISABLE; \
+ INIT_RNMI; \
INIT_SATP; \
INIT_PMP; \
DELEGATE_NO_TRAPS; \
diff --git a/v/entry.S b/v/entry.S
index 3388ffb..13d46a3 100644
--- a/v/entry.S
+++ b/v/entry.S
@@ -60,6 +60,8 @@ handle_reset:
li x30, 0
li x31, 0
+ INIT_RNMI
+
la t0, trap_vector
csrw mtvec, t0
la sp, STACK_TOP - SIZEOF_TRAPFRAME_T