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authorAndrew Waterman <waterman@cs.berkeley.edu>2016-03-02 23:19:25 -0800
committerAndrew Waterman <waterman@cs.berkeley.edu>2016-03-02 23:19:25 -0800
commitb7528b89c8673bf38e5e4ec1e8f037ec2bcbee24 (patch)
tree8bb1a13503413528f7fea4f1bb3bf39acfe851eb /p/riscv_test.h
parenta6dae9f422fc86a6459d26b71672e1cb55a4fc22 (diff)
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WIP on priv spec v1.9
Diffstat (limited to 'p/riscv_test.h')
-rw-r--r--p/riscv_test.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h
index c4df61e..cdc256e 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -121,16 +121,15 @@ reset_vector: \
la t0, stvec_handler; \
beqz t0, 1f; \
csrw stvec, t0; \
- li t0, (1 << CAUSE_MISALIGNED_LOAD) | \
- (1 << CAUSE_MISALIGNED_STORE) | \
- (1 << CAUSE_MISALIGNED_FETCH) | \
- (1 << CAUSE_FAULT_LOAD) | \
+ li t0, (1 << CAUSE_FAULT_LOAD) | \
(1 << CAUSE_FAULT_STORE) | \
(1 << CAUSE_FAULT_FETCH) | \
- (1 << CAUSE_ILLEGAL_INSTRUCTION) | \
+ (1 << CAUSE_MISALIGNED_FETCH) | \
(1 << CAUSE_USER_ECALL) | \
(1 << CAUSE_BREAKPOINT); \
csrw medeleg, t0; \
+ csrr t1, medeleg; \
+ bne t0, t1, other_exception; \
1: csrwi mstatus, 0; \
init; \
EXTRA_INIT; \