From b7528b89c8673bf38e5e4ec1e8f037ec2bcbee24 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 2 Mar 2016 23:19:25 -0800 Subject: WIP on priv spec v1.9 --- p/riscv_test.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'p/riscv_test.h') diff --git a/p/riscv_test.h b/p/riscv_test.h index c4df61e..cdc256e 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -121,16 +121,15 @@ reset_vector: \ la t0, stvec_handler; \ beqz t0, 1f; \ csrw stvec, t0; \ - li t0, (1 << CAUSE_MISALIGNED_LOAD) | \ - (1 << CAUSE_MISALIGNED_STORE) | \ - (1 << CAUSE_MISALIGNED_FETCH) | \ - (1 << CAUSE_FAULT_LOAD) | \ + li t0, (1 << CAUSE_FAULT_LOAD) | \ (1 << CAUSE_FAULT_STORE) | \ (1 << CAUSE_FAULT_FETCH) | \ - (1 << CAUSE_ILLEGAL_INSTRUCTION) | \ + (1 << CAUSE_MISALIGNED_FETCH) | \ (1 << CAUSE_USER_ECALL) | \ (1 << CAUSE_BREAKPOINT); \ csrw medeleg, t0; \ + csrr t1, medeleg; \ + bne t0, t1, other_exception; \ 1: csrwi mstatus, 0; \ init; \ EXTRA_INIT; \ -- cgit v1.1