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2019-07-29Support RV32E. Fixed #198 (#200)Leway Colin3-42/+42
2019-04-20masking no longer required.Neel1-16/+0
2019-04-20removing check for reset value of type in mcontrolNeel1-10/+8
2019-04-20fix for #159 #158Neel1-4/+7
2019-03-17Rename TEST_SRL to TEST_SRLI to avoid conflicts with another TEST_SRL (#183)Pavel I. Kryukov1-18/+18
2019-01-26Fix comments for shift amount. (#177)takeoverjp3-3/+3
2018-12-18Avoid using t3 and t4 for supporting RV32E (#173)zhonghochen1-5/+6
2018-11-16Test memory content on failing SC (#171)Florian Zaruba1-4/+10
2018-09-08RV64 s{ll,ra,rl}w tests with non-canonical valuesTommy Thorn6-0/+42
2018-09-06Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ↵Andrew Waterman1-1/+1
(#159)" This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028, under the advisement of @tommythorn in #158.
2018-09-06breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)Tommy Thorn1-1/+1
2018-08-21Changing the register mstatus is read into (#152)Srivatsa Yogendra1-2/+2
The mstatus reading overwrites the expected user mode cause value.
2018-08-20Revert "Fix to solve the failing tests shamt, csr and scall (#151)"Andrew Waterman2-52/+5
This reverts commit 31a91823b7c7becacd06c9c32e44180eea5e4fe7. These changes should be made to the test environment, not the tests themselves.
2018-08-17Fix to solve the failing tests shamt, csr and scall (#151)Srivatsa Yogendra2-5/+52
* making mtvec_handler global * Adding the pmp configuration inst The PMP config instructions are added as the test jumps to user mode * Adding pmp config inst Adding pmp config instructions as the test jumps to user mode * changing to PMP macros * changing to PMP Macros * moving the #endif after pmp initialization * Removing the unwanted label
2018-08-17making mtvec_handler global (#150)Srivatsa Yogendra1-0/+1
2018-07-09Check that SC yields the load reservationAndrew Waterman1-0/+9
https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612
2018-04-30[rv64ua/lrsc] Initialize memory read out. (#135)Christopher Celio1-1/+3
* [rv64ua/lrsc] Initialize memory read out. Even though the load contents are discarded, this un-initialized memory value can lead to a divergence for co-simulation between two different RISC-V designs. * [rv64ua/lrsc] Use .skip instead of .align.
2018-04-09Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121)Andrei Tatarnikov1-3/+3
2018-03-21Make misa.C test conform to Hauser proposalAndrew Waterman1-43/+10
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7
2018-02-27Add test for clearing misa.C while PC is misaligned (#117)Andrew Waterman1-1/+79
See https://github.com/riscv/riscv-isa-manual/pull/139
2018-01-02Test access exception behavior for illegal addresses (#111)Andrew Waterman2-0/+71
OK'd by @palmer-dabbelt
2017-11-27Rename sbadaddr to satpAndrew Waterman2-3/+3
2017-11-26Rv32ud tests (#108)Torbjørn23-0/+318
* Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32
2017-11-22Check sepc for rv64si/scall test. (#107)Christopher Celio1-0/+4
Closes #105.
2017-11-20Check mtval in rv64mi-p-illegal (#104)Andrew Waterman1-0/+11
Closes #103
2017-11-11Make sure that code is 4-byte aligned before disabling rvc (#100)Andrew Waterman4-1/+5
2017-11-09Make rv64mi-p-ecall work when U-mode is not presentAndrew Waterman1-1/+17
2017-11-09Use mstatus.MPP to check existence of U-modeAndrew Waterman1-5/+6
misa is allowed to be hardwired to 0, so checking its U bit could incorrectly suggest that U-mode is not supported.
2017-11-01SBREAK test now checks EPC value. (#92)Christopher Celio1-0/+4
Closes #89
2017-10-30Remove cache miss test from last AMO test. (#88)Richard Xia1-17/+0
Follow-up to b68b39031a730ecc155ed87fba2ed5f111d0ab07. The 64KiB allocated by the code to force a cache miss makes it impossible to run the test from any memories that are smaller 64KiB, such as scratchpad memories or LIMs. Since this is trying to test microarchitectural behavior, they don't belong in these ISA tests anyway.
2017-10-30Declare trap handlers as global symbols. (#87)Richard Xia8-0/+9
This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit.
2017-10-26Verify that mtval/stval is written correctly on misaligned fetchAndrew Waterman1-1/+9
2017-10-26Fix rv64mi-csr for the case where U-mode is not available. (#86)Richard Xia1-0/+16
2017-09-01Improve ma_fetch test to cover JAL and branchesAndrew Waterman1-1/+48
2017-08-07rv64[ms]i-csr: Only emit F instructions when compiled for F.Richard Xia1-1/+6
2017-08-04RV32 div tests should use -2^31 for min value, not -2^63Andrew Waterman3-9/+9
2017-08-04Improve RVC testAndrew Waterman1-3/+2
Make the page-crossing instruction non-idempotent to detect erroneously executing the first 16 bits of the instruction with garbage MSBs.
2017-05-22minNum -> minimumNumberAndrew Waterman2-4/+16
2017-05-17Manually assemble bad shift amount, since assembler rejectsAndrew Waterman1-1/+1
Resolves #51
2017-05-05Check UXL in sstatusAndrew Waterman1-0/+5
2017-05-05Test that superpage PTEs trap when PPN LSBs are setAndrew Waterman1-0/+18
2017-05-05Regularize control flow in dirty-bit testAndrew Waterman1-8/+12
2017-04-14Fix illegal-instruction test when S-mode is not implementedAndrew Waterman1-10/+14
2017-04-10Improve fp ldst/move tests; remove redundant fsgnj testsAndrew Waterman9-122/+126
2017-04-07Retrofit rv64mi-p-illegal to test vectored interruptsAndrew Waterman1-7/+41
2017-04-07Remove defunct IPI testsAndrew Waterman4-62/+0
2017-04-05Make ma_addr test work for systems with misaligned ld/stAndrew Waterman1-34/+66
2017-03-30Expand dirty-bit test to test MPRV and SUMAndrew Waterman1-27/+30
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-1/+1
2017-03-22Clean up benchmarks buildAndrew Waterman1-2/+0
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