| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2016-08-30 | Add missing RV32 slt[i]u tests | Andrew Waterman | 1 | -1/+1 |
| 2016-07-11 | Remove vestigial j instruction test; improve jal test | Andrew Waterman | 1 | -1/+1 |
| 2016-06-22 | separate ua and um tests from ui testssplit-isa-tests | Howard Mao | 1 | -5/+0 |
| 2016-05-22 | Enable LR/SC tests, even for uniprocessors | Andrew Waterman | 1 | -3/+1 |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 1 | -3/+1 |
| 2016-03-14 | More RV32 tests | Andrew Waterman | 1 | -2/+3 |
| 2015-03-16 | revamp vector tests with new privileged spec, and add scalar pt tests | Yunsup Lee | 1 | -2/+3 |
| 2014-08-28 | Added "simple" test to rv32ui. | Christopher Celio | 1 | -0/+1 |
| 2014-01-23 | Done with rv32ui asm test ports | Eric Love | 1 | -2/+2 |
| 2014-01-23 | Fixed srl, srli | Eric Love | 1 | -1/+1 |
| 2014-01-23 | srl and srai | Eric Love | 1 | -2/+2 |
| 2014-01-23 | First round of rv32ui asm tests | Eric Love | 1 | -15/+15 |
| 2013-07-25 | Remove JALR static hints | Andrew Waterman | 1 | -1/+1 |
| 2013-04-29 | add first RV32 tests | Andrew Waterman | 1 | -0/+33 |
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index : rocket-tools/riscv-tests.git | |
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