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AgeCommit message (Expand)AuthorFilesLines
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome3-7/+10
2018-10-03Added tests for hw and sw watchpointscgsfv3-0/+88
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-09-13Put debug test stack in data instead of textTim Newsome1-0/+1
2018-09-03Merge pull request #156 from riscv/PrivChangeTim Newsome1-27/+26
2018-08-31Fix CustomRegisterTest.Tim Newsome2-5/+6
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome12-0/+55
2018-08-28Reset address translation/perms before PrivChangeTim Newsome1-27/+26
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome2-3/+4
2018-08-23Get all of the log into the final log fileTim Newsome1-6/+20
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
2018-08-22Add debug test, which checks that openocd correctly switch active thread on a...Dmitry Ryzhov1-0/+28
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
2018-06-18Add reproduce line to the end of debug test logsTim Newsome1-0/+2
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome2-23/+46
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs2-21/+11
2018-05-14Make DownloadTest properly park other harts.Tim Newsome2-5/+9
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-05-11debug: output some more useful info into the post-mortem dataMegan Wachs1-0/+5
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
2018-04-27Merge pull request #125 from riscv/debug-delete-simMegan Wachs1-17/+0
2018-04-27debug: add missing align directive on trap_entrytrap_entry_align-1Megan Wachs1-0/+1
2018-04-24Fix race when making logs directoryTim Newsome1-1/+5
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
2018-04-09Compute gdb command timeout based on ops estimateTim Newsome2-14/+18
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome4-0/+6
2018-03-27Test debug authentication.Tim Newsome4-3/+19
2018-03-23Print log filename at the end of the log.Tim Newsome1-0/+1
2018-03-01Test debugging with/without a program bufferTim Newsome5-5/+10
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome5-0/+29
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome3-10/+9
2018-02-07Link scripts shouldn't be executable.Tim Newsome1-0/+0
2018-01-08Deal with gdb reporting pmpcfg0 not existing.Tim Newsome2-3/+16
2018-01-05Add test for multicore failureTim Newsome2-5/+40
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome6-8/+20
2017-12-21Add all-tests target.Tim Newsome1-1/+3
2017-12-20Remove `set arch riscv:rv%d`Tim Newsome1-1/+0
2017-12-20Verify that F18 does not exist on FPU-less targetsTim Newsome1-17/+20
2017-12-12Display env variables used when invoking OpenOCDTim Newsome1-1/+6
2017-12-01Ensure there are no unnamed registers.Tim Newsome1-0/+2
2017-11-30Clean up VcsSim init()Tim Newsome1-2/+12
2017-11-27Rename sbadaddr to satpAndrew Waterman1-3/+3
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