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path: root/debug/testlib.py
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2018-04-09Compute gdb command timeout based on ops estimateTim Newsome1-13/+17
The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122.
2018-03-27Test debug authentication.Tim Newsome1-0/+1
Also halt instead of reset spike targets, which tests a more complicated code path.
2018-03-23Print log filename at the end of the log.Tim Newsome1-0/+1
This makes it much easier to look at a log if you see a failure scrolling by on your terminal.
2018-03-01Test debugging with/without a program bufferTim Newsome1-1/+6
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome1-0/+1
2018-01-08Deal with gdb reporting pmpcfg0 not existing.Tim Newsome1-0/+9
It's an optional register.
2018-01-05Add test for multicore failureTim Newsome1-5/+12
Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1.
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome1-4/+8
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-12-20Remove `set arch riscv:rv%d`Tim Newsome1-1/+0
gdb gets target XLEN from register width now, so this is taken care of automatically.
2017-12-12Display env variables used when invoking OpenOCDTim Newsome1-1/+6
This makes it a little easier to just cut and paste from the log when reproducing a failure. (The port number still needs changing though.)
2017-11-30Clean up VcsSim init()Tim Newsome1-2/+12
Use a unique log file, so you can run multiple instances at once. Add time out to waiting for the simulator to be ready.
2017-11-19Ensure log file is fully written before reading itTim Newsome1-0/+1
Fixes --print-failures sometimes not actually printing out details about failures.
2017-11-19Make pylint happy.Tim Newsome1-2/+3
2017-11-16Debug: Use the --32 and --64 command line arguments (#97)Megan Wachs1-6/+12
* Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer
2017-11-02Add --print-log-names to print temp log names ASAPTim Newsome1-5/+15
When not passed, they are no longer printed out.
2017-11-02Ensure gdb connection failures end up in main log.Tim Newsome1-9/+18
2017-11-02debug: Need to apply remotetimeout before connecting to remote target (#94)Megan Wachs1-6/+7
* debug: Need to apply remotetimeout before connecting to remote target * debug: whitespace cleanup
2017-11-01Make pylint 1.6.5 happy.Tim Newsome1-2/+1
2017-11-01Fix MulticoreRegTest.Tim Newsome1-1/+11
This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume.
2017-10-04Merge pull request #79 from riscv/multigdbTim Newsome1-79/+168
Multigdb support
2017-09-29Make ExamineTarget multi-core aware.Tim Newsome1-18/+23
Now on multi-core targets it only runs once, wasting less time.
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome1-70/+168
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-22Remove unused function.Tim Newsome1-9/+0
2017-09-15Don't read entire log into RAM just to print it.Tim Newsome1-2/+1
2017-09-14misa is stored in the hart now, not the targetTim Newsome1-6/+6
2017-09-14When spike fails to launch, display its output.Tim Newsome1-21/+29
2017-09-14Call postMortem() when a test fails.Tim Newsome1-0/+10
2017-09-14Clarify timeout units.Tim Newsome1-0/+1
2017-09-01Add some infrastructure for multicore tests.Tim Newsome1-2/+2
When compiling, define the number of harts. This means we only need to allocate a lot of stack if there are a lot of harts.
2017-08-28Fix rebase bug.Tim Newsome1-1/+3
2017-08-28WIP multicore testing.Tim Newsome1-6/+20
2017-08-28WIP towards multiple gdb instances.Tim Newsome1-4/+14
2017-08-28Make the debug tests aware of multicore.Tim Newsome1-30/+65
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-14Put logfile code back so everything works again.Tim Newsome1-2/+3
I don't exactly understand why it has to be the way it is, but I just want it to work. Also fix a pylint complaint.
2017-08-14debug: clean up Temporary Log File messagesMegan Wachs1-2/+2
2017-08-14debug: Avoid None type errorMegan Wachs1-1/+1
2017-08-14debug: Revert change to print backtrace, as that is actually already printedMegan Wachs1-2/+0
2017-08-14debug: Allow OpenOCD startup timeout to be specified. Print out path to log ↵Megan Wachs1-4/+5
files.
2017-08-14When a test fails with exception, actually print out the reason why.Megan Wachs1-0/+2
2017-08-11Show the OpenOCD log in all(?) failure cases.Tim Newsome1-23/+29
2017-08-11Print out name of logfile when debug test is run.Tim Newsome1-5/+5
2017-08-11When make fails to run a test, print out the log.Tim Newsome1-1/+4
2017-08-10Give these sim targets a chance of passing.Tim Newsome1-2/+4
Also make sure vsim.log makes it into the generated log file.
2017-07-27Make pylint happy.Tim Newsome1-2/+2
2017-07-26Use new OpenOCD messages to determine gdb port.Tim Newsome1-41/+8
This is simpler and more reliable than playing around with lsof. Specifically, it works if the OpenOCD command is "strace openocd" while the previous code did not.
2017-07-12Print out logs in more failure cases.Tim Newsome1-4/+10
2017-07-03Add gdb_setup to target for arbitrary gdb commandsTim Newsome1-0/+3
I'm using this for a target where misa is at an old address, to set riscv use_compressed_breakpoints off
2017-06-26Move target definition into individual files.Tim Newsome1-4/+5
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.
2017-06-22Add basic multicore test.Tim Newsome1-8/+29
2017-06-20Smoketest multicore.Tim Newsome1-5/+15
When connecting to gdb, select a random thread and use that for the current test. Also replace infinite_loop with something that will later allow smoketesting of more than one thread.