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rocket-tools/riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
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misc
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python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
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Author
Files
Lines
2017-10-24
Increase dual-core RV64 timeouts.
Tim Newsome
2
-2
/
+2
2017-09-29
Fix tests to work in multi-gdb mode.
Tim Newsome
9
-4
/
+48
2017-09-21
Add coverage for single-core non-rtos OpenOCD.
Tim Newsome
4
-3
/
+19
2017-09-19
Allow multiple reset vectors.
Tim Newsome
2
-2
/
+2
2017-09-01
Use 32-bit link script for 32-bit target.
Tim Newsome
1
-1
/
+1
2017-08-28
This file isn't ready yet.
Tim Newsome
1
-11
/
+0
2017-08-28
Increase remotetimeout for spike targets.
Tim Newsome
5
-0
/
+15
2017-08-28
Make pylint happy.
Tim Newsome
3
-3
/
+3
2017-08-28
WIP multicore testing.
Tim Newsome
4
-0
/
+8
2017-08-28
Make the debug tests aware of multicore.
Tim Newsome
11
-38
/
+63
2017-08-10
Give these sim targets a chance of passing.
Tim Newsome
2
-3
/
+7
2017-06-26
Move target definition into individual files.
Tim Newsome
21
-148
/
+74
2017-06-15
Test 64-bit addressing.
Tim Newsome
4
-0
/
+53
2017-06-09
Add final echo to E300/U500 OpenOCD scripts
Tim Newsome
2
-0
/
+2
2017-06-09
Make HiFive1 testing (mostly) work again
Tim Newsome
2
-2
/
+5
2017-05-16
Link the infinate loop at 0x10000000
Palmer Dabbelt
1
-1
/
+1
2017-05-16
debug: Update OpenOCD configs.
Megan Wachs
2
-5
/
+4
2017-05-15
Don't use the RTOS, and do "reset halt"
Palmer Dabbelt
1
-3
/
+4
2017-04-18
debug: Don't halt out of reset. It's unrealistic. Use a program which loops (...
Megan Wachs
1
-1
/
+2
2017-04-18
debug: Use RTOS OpenOCD for Spike for now.
Megan Wachs
1
-1
/
+1
2017-04-17
Merge remote-tracking branch 'origin/newprogram' into debug-0.13
Megan Wachs
5
-7
/
+10
2017-04-17
Merge remote-tracking branch 'origin/priv-1.10' into HEAD
Megan Wachs
5
-5
/
+5
2017-04-14
debug: checkpoint of trying to get simulation tests working
Megan Wachs
5
-5
/
+7
2017-04-14
debug: working with newprogram branch
Megan Wachs
2
-3
/
+4
2017-03-29
Change the global pointer symbol to __global_pointer$
Palmer Dabbelt
5
-5
/
+5
2017-03-03
Resurrect spike debug support
Palmer Dabbelt
1
-0
/
+17
2017-02-17
Add HiFive1 target.
Tim Newsome
2
-0
/
+57
2016-10-18
Pull port number from VCS output and pass to OpenOCD.
Richard Xia
2
-0
/
+2
2016-10-03
Add test for memory read from invalid address.
Tim Newsome
1
-0
/
+2
2016-08-11
Add FreedomU500 & incorporate feedback
Megan Wachs
5
-18
/
+47
2016-08-08
Add U500 Target
Megan Wachs
2
-0
/
+53
2016-08-08
Added FreedomE300 Simulator target
Megan Wachs
2
-0
/
+53
2016-07-27
Rename m2gl_m2s to freedom-e300.
Tim Newsome
2
-0
/
+0
2016-07-19
I think I've finally got malloc working right.
Tim Newsome
2
-4
/
+7
2016-07-18
Increase TCK speed.
Tim Newsome
1
-1
/
+1
2016-07-18
Bump up speed.
Tim Newsome
1
-1
/
+1
2016-07-18
Update IDCODE.
Tim Newsome
1
-1
/
+1
2016-07-18
Add simple register tests.
Tim Newsome
1
-1
/
+1
2016-07-18
Add block test.
Tim Newsome
2
-5
/
+4
2016-07-18
All tests pass with spike now.
Tim Newsome
2
-262
/
+0
2016-07-18
Made some progress towards working with spike.
Tim Newsome
2
-0
/
+166
2016-07-18
WIP on debug testing.
Tim Newsome
3
-0
/
+183