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debug
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gdbserver.py
Age
Commit message (
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Author
Files
Lines
2020-08-31
Add test for `riscv repeat_read`. (#293)
Tim Newsome
1
-0
/
+34
2020-06-25
Add manual hwbp test. (#283)
Tim Newsome
1
-0
/
+92
2020-06-25
Create a more sophisticated vector test (#284)
Tim Newsome
1
-1
/
+61
2020-05-26
Test semihosting calls (#280)
Tim Newsome
1
-0
/
+32
2020-04-10
Make TooManyHwbp more thorough. (#272)
Tim Newsome
1
-1
/
+6
2020-03-26
Improve address translation tests (#261)
Tim Newsome
1
-14
/
+27
2020-03-26
Write a NOP program in PrivRw test. (#260)
Tim Newsome
1
-9
/
+2
2020-02-14
Add tests for vector register access (#244)
Tim Newsome
1
-0
/
+21
2020-02-11
Generate very different values on different harts. (#238)
Tim Newsome
1
-4
/
+4
2020-02-11
Look for \bmain\b instead of ' main '. (#237)
Tim Newsome
1
-2
/
+2
2020-01-15
Force DMI busy in all tests. (#235)
Tim Newsome
1
-9
/
+26
2020-01-09
Smoke test virtual address translation support. (#233)
Tim Newsome
1
-0
/
+49
2019-12-18
Hardcode misa values for all spike targets. (#227)
Tim Newsome
1
-0
/
+8
2019-11-22
Move to Python 3. (#218)
Tim Newsome
1
-34
/
+36
2019-10-15
Add support to run all tests against HiFive Unleashed. (#212)
Tim Newsome
1
-2
/
+4
2019-08-02
Miscellaneous minor test improvements (#199)
Tim Newsome
1
-8
/
+7
2019-07-15
Make tests work with RV32E targets. (#196)
Tim Newsome
1
-1
/
+4
2019-06-14
Work better with mainline gdb (#192)
Tim Newsome
1
-8
/
+8
2019-04-04
Test simultaneous resume using hasel. (#186)
Tim Newsome
1
-8
/
+13
2019-03-11
Add SmpSimultaneousRunHalt test. (#181)
Tim Newsome
1
-0
/
+49
2019-02-14
Test `-rtos hwthread` (#178)
Tim Newsome
1
-10
/
+12
2019-01-07
Fail on unsupported SREC type.
Tim Newsome
1
-0
/
+2
2018-12-31
Fix MemTestBlock
Tim Newsome
1
-20
/
+41
2018-12-03
Reduce download size a bit.
Tim Newsome
1
-4
/
+8
2018-11-30
Use more than 1KB for download test.
Tim Newsome
1
-1
/
+1
2018-11-16
Make pylint happy.
Tim Newsome
1
-3
/
+6
2018-11-14
Merge pull request #165 from riscv/flash
Tim Newsome
1
-13
/
+33
2018-11-14
Cleanup and renamed test flag to invalid_memory_returns_zero
cgsfv
1
-2
/
+2
2018-11-13
Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix
cgsfv
1
-0
/
+52
2018-10-31
Fix remaining tests to work from flash:
Tim Newsome
1
-4
/
+12
2018-10-29
Almost all tests pass with HiFive1-flash
Tim Newsome
1
-3
/
+12
2018-10-29
Tweak debug tests to run out of flash.
Tim Newsome
1
-6
/
+9
2018-10-24
Merge branch 'TriggerLoadAddressInstant'
Tim Newsome
1
-12
/
+1
2018-10-24
Re-enable TriggerStoreAddressInstant
Tim Newsome
1
-12
/
+1
2018-10-05
Make HwWatchpoint test fail on incorrect result.
hw_watchpoint
Tim Newsome
1
-5
/
+8
2018-10-03
Added tests for hw and sw watchpoints
cgsfv
1
-0
/
+56
2018-09-03
Merge pull request #156 from riscv/PrivChange
Tim Newsome
1
-27
/
+26
2018-08-31
Fix CustomRegisterTest.
Tim Newsome
1
-1
/
+2
2018-08-29
Add test case for `riscv expose_custom`.
Tim Newsome
1
-0
/
+30
2018-08-28
Reset address translation/perms before PrivChange
Tim Newsome
1
-27
/
+26
2018-08-27
Neuter TriggerStoreAddressInstant
Tim Newsome
1
-1
/
+13
2018-08-27
Make pylint happy.
Tim Newsome
1
-1
/
+2
2018-08-25
Temporarily disabling PrivChange test
Andrew Waterman
1
-22
/
+23
2018-08-23
Make pylint happy with change d1d2d953b5016b465.
Tim Newsome
1
-2
/
+3
2018-08-23
Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread
Tim Newsome
1
-0
/
+28
2018-08-22
Disable MulticoreRunHaltStepiTest
Tim Newsome
1
-52
/
+52
2018-08-22
Add debug test, which checks that openocd correctly switch active thread on a...
Dmitry Ryzhov
1
-0
/
+28
2018-08-13
Add jump/hbreak test.
Tim Newsome
1
-0
/
+23
2018-07-03
rwatch/watch on explicit address
Tim Newsome
1
-2
/
+4
2018-05-18
Fix MulticoreRunHaltStepiTest
Tim Newsome
1
-19
/
+37
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