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AgeCommit message (Expand)AuthorFilesLines
2013-11-19Add rv64uv-p-amoxor_{w,d} testsQuan Nguyen3-2/+118
2013-11-19fix rv64uv/vvadd_fd test to correctly check resultsYunsup Lee1-2/+2
2013-11-13added riscv-test-env as a submoduleYunsup Lee2-0/+8
2013-11-13split out envs from riscv-testsYunsup Lee12-1200/+0
2013-11-05add accelerator disabled causeYunsup Lee1-0/+1
2013-11-05correctly set SR_EA bit for all vector physical supervisor testsYunsup Lee12-0/+14
2013-11-05correctly set SR_EA bit for all vector physical testsYunsup Lee61-61/+64
2013-10-18revamp pt tests as wellYunsup Lee7-40/+31
2013-10-18hwacha virtual tests workingYunsup Lee7-44/+86
2013-10-17add hwacha exception supportYunsup Lee20-122/+448
2013-10-17disable vector bank testsYunsup Lee3-594/+594
2013-10-17add passing physical vector tests back inYunsup Lee4-5/+4
2013-10-17update out-of-date floating-point test in rv64uvYunsup Lee1-1/+1
2013-10-17fix broken amoor_w rv64uv testYunsup Lee1-0/+3
2013-10-10Merge branch 'master' of github.com:ucb-bar/riscv-testsChristopher Celio69-1837/+1795
2013-10-10Benchmarks now run in user-mode.Christopher Celio10-114/+104
2013-10-10revamp hwacha testsYunsup Lee69-1837/+1795
2013-09-21Re-enable virtual memory testsAndrew Waterman3-8/+15
2013-09-21New AUIPC semanticsAndrew Waterman1-6/+12
2013-09-15Don't emit vector instructions for nowAndrew Waterman2-0/+4
2013-09-11Add AMOXOR testAndrew Waterman3-2/+128
2013-08-25Don't build vector benchmarks for nowAndrew Waterman1-3/+3
2013-08-24don't emit vvcfg for nowAndrew Waterman2-3/+3
2013-08-23Add autoconf-generated configureAndrew Waterman2-0/+3478
2013-08-23Reflect changes to ISAAndrew Waterman47-2570/+487
2013-08-23Merge pull request #1 from smirolo/configureSebastien Mirolo6-14/+60
2013-08-12Merge branch 'master' of git://github.com/ucb-bar/riscv-tests into configureSebastien Mirolo4-174/+2
2013-07-25Remove JALR static hintsAndrew Waterman4-174/+2
2013-07-24feature: add autoconfSebastien Mirolo6-14/+60
2013-06-14removed bad mt testHenry Cook1-1/+0
2013-06-13multithreading tests from 152 lab 5Henry Cook285-0/+60428
2013-06-10Don't disassemble zerosAndrew Waterman1-1/+1
2013-05-16add failing multiply testYunsup Lee1-0/+3
2013-05-13change riscv-isa-run to spikeYunsup Lee2-2/+2
2013-05-02use RVTEST_RV64UF macro for FPU testsAndrew Waterman14-14/+32
2013-05-01pass all FP tests if FPU not presentAndrew Waterman5-18/+17
2013-04-29add first RV32 testsAndrew Waterman13-7/+637
2013-04-29add benchmarks gitignoreYunsup Lee1-0/+6
2013-04-29benchmarks initial commitYunsup Lee71-0/+33853
2013-04-24add gitignoreYunsup Lee1-0/+1
2013-04-24cleanup Makefiles in isaYunsup Lee11-606/+220
2013-04-24add missing RVTEST_CODE_END macrosYunsup Lee3-0/+6
2013-04-24add more header information to test_macrosYunsup Lee2-183/+225
2013-04-24change label names to avoid conflicts with test codeYunsup Lee1-19/+19
2013-04-22get rid of RVTEST_PASS_NOFPYunsup Lee5-29/+0
2013-04-22initial commitYunsup Lee189-0/+44573
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