initial commit

189 files changed, 44573 insertions, 0 deletions

diff --git a/env/p/link.ld b/env/p/link.ld
new file mode 100644
index 0000000..6b19389
--- /dev/null
+++ b/env/p/link.ld
@@ -0,0 +1,44 @@
+/*======================================================================*/
+/* Proxy kernel linker script                                           */
+/*======================================================================*/
+/* This is the linker script used when building the proxy kernel. */
+
+/*----------------------------------------------------------------------*/
+/* Setup                                                                */
+/*----------------------------------------------------------------------*/
+
+/* The OUTPUT_ARCH command specifies the machine architecture where the
+   argument is one of the names used in the BFD library. More
+   specifically one of the entires in bfd/cpu-mips.c */
+
+OUTPUT_ARCH( "riscv" )
+
+/* The ENTRY command specifies the entry point (ie. first instruction
+   to execute). The symbol _start should be defined in each test. */
+
+ENTRY( _start )
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+SECTIONS
+{
+
+  /* text: test code section */
+  . = 0x00002000;
+  .text :
+  {
+    *(.text)
+  }
+
+  /* data: Initialized data segment */
+  .data :
+  {
+    *(.data)
+  }
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h
new file mode 100644
index 0000000..a4f9668
--- /dev/null
+++ b/env/p/riscv_test.h
@@ -0,0 +1,76 @@
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
+#define _ENV_PHYSICAL_SINGLE_CORE_H
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U                                                    \
+
+#define RVTEST_RV64S                                                    \
+
+#define RVTEST_FP_ENABLE                                                \
+  setpcr cr0, 2;                                                        \
+  mfpcr a0, cr0;                                                        \
+  and   a0, a0, 2;                                                      \
+  beqz  a0, 1f;                                                         \
+  mtfsr x0;                                                             \
+1:
+
+#define RVTEST_PASS_NOFP                                                \
+  RVTEST_FP_ENABLE                                                      \
+  bnez a0, 2f;                                                          \
+  RVTEST_PASS                                                           \
+2:                                                                      \
+
+#define RVTEST_VEC_ENABLE                                               \
+  mfpcr a0, cr0;                                                        \
+  ori   a0, a0, 4;                                                      \
+  mtpcr a0, cr0;                                                        \
+  li    a0, 0xff;                                                       \
+  mtpcr a0, cr18;                                                       \
+
+#define RVTEST_CODE_BEGIN                                               \
+        .text;                                                          \
+        .align  4;                                                      \
+        .global _start;                                                 \
+_start:                                                                 \
+        RVTEST_FP_ENABLE                                                \
+        RVTEST_VEC_ENABLE                                               \
+        mfpcr a0, cr10; 1: bnez a0, 1b;                                 \
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END                                                 \
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS                                                     \
+        fence;                                                          \
+        li  x1, 1;                                                      \
+        mtpcr x1, cr30;                                                 \
+1:      b 1b;                                                           \
+
+#define RVTEST_FAIL                                                     \
+        fence;                                                          \
+        beqz x28, 1f;                                                   \
+        sll x28, x28, 1;                                                \
+        or x28, x28, 1;                                                 \
+        mtpcr x28, cr30;                                                \
+1:      b 1b;                                                           \
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_DATA_BEGIN
+#define RVTEST_DATA_END
+
+//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
+//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+
+#endif
diff --git a/env/pm/link.ld b/env/pm/link.ld
new file mode 100644
index 0000000..6b19389
--- /dev/null
+++ b/env/pm/link.ld
@@ -0,0 +1,44 @@
+/*======================================================================*/
+/* Proxy kernel linker script                                           */
+/*======================================================================*/
+/* This is the linker script used when building the proxy kernel. */
+
+/*----------------------------------------------------------------------*/
+/* Setup                                                                */
+/*----------------------------------------------------------------------*/
+
+/* The OUTPUT_ARCH command specifies the machine architecture where the
+   argument is one of the names used in the BFD library. More
+   specifically one of the entires in bfd/cpu-mips.c */
+
+OUTPUT_ARCH( "riscv" )
+
+/* The ENTRY command specifies the entry point (ie. first instruction
+   to execute). The symbol _start should be defined in each test. */
+
+ENTRY( _start )
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+SECTIONS
+{
+
+  /* text: test code section */
+  . = 0x00002000;
+  .text :
+  {
+    *(.text)
+  }
+
+  /* data: Initialized data segment */
+  .data :
+  {
+    *(.data)
+  }
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
diff --git a/env/pm/riscv_test.h b/env/pm/riscv_test.h
new file mode 100644
index 0000000..102e6e0
--- /dev/null
+++ b/env/pm/riscv_test.h
@@ -0,0 +1,75 @@
+#ifndef _ENV_PHYSICAL_MULTI_CORE_H
+#define _ENV_PHYSICAL_MULTI_CORE_H
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U                                                    \
+
+#define RVTEST_RV64S                                                    \
+
+#define RVTEST_FP_ENABLE                                                \
+  setpcr cr0, 2;                                                        \
+  mfpcr a0, cr0;                                                        \
+  and   a0, a0, 2;                                                      \
+  beqz  a0, 1f;                                                         \
+  mtfsr x0;                                                             \
+1:
+
+#define RVTEST_PASS_NOFP                                                \
+  RVTEST_FP_ENABLE                                                      \
+  bnez a0, 2f;                                                          \
+  RVTEST_PASS                                                           \
+2:                                                                      \
+
+#define RVTEST_VEC_ENABLE                                               \
+  mfpcr a0, cr0;                                                        \
+  ori   a0, a0, 4;                                                      \
+  mtpcr a0, cr0;                                                        \
+  li    a0, 0xff;                                                       \
+  mtpcr a0, cr18;                                                       \
+
+#define RVTEST_CODE_BEGIN                                               \
+        .text;                                                          \
+        .align  4;                                                      \
+        .global _start;                                                 \
+_start:                                                                 \
+        RVTEST_FP_ENABLE                                                \
+        RVTEST_VEC_ENABLE                                               \
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END                                                 \
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_FAIL                                                     \
+        fence;                                                          \
+        beqz x28, 1f;                                                   \
+        sll x28, x28, 1;                                                \
+        or x28, x28, 1;                                                 \
+        mtpcr x28, cr30;                                                \
+1:      b 1b;                                                           \
+
+#define RVTEST_PASS                                                     \
+        fence;                                                          \
+        li  x1, 1;                                                      \
+        mtpcr x1, cr30;                                                 \
+1:      b 1b;                                                           \
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_DATA_BEGIN
+#define RVTEST_DATA_END
+
+//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
+//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+
+#endif
diff --git a/env/pt/link.ld b/env/pt/link.ld
new file mode 100644
index 0000000..6b19389
--- /dev/null
+++ b/env/pt/link.ld
@@ -0,0 +1,44 @@
+/*======================================================================*/
+/* Proxy kernel linker script                                           */
+/*======================================================================*/
+/* This is the linker script used when building the proxy kernel. */
+
+/*----------------------------------------------------------------------*/
+/* Setup                                                                */
+/*----------------------------------------------------------------------*/
+
+/* The OUTPUT_ARCH command specifies the machine architecture where the
+   argument is one of the names used in the BFD library. More
+   specifically one of the entires in bfd/cpu-mips.c */
+
+OUTPUT_ARCH( "riscv" )
+
+/* The ENTRY command specifies the entry point (ie. first instruction
+   to execute). The symbol _start should be defined in each test. */
+
+ENTRY( _start )
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+SECTIONS
+{
+
+  /* text: test code section */
+  . = 0x00002000;
+  .text :
+  {
+    *(.text)
+  }
+
+  /* data: Initialized data segment */
+  .data :
+  {
+    *(.data)
+  }
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
diff --git a/env/pt/pcr.h b/env/pt/pcr.h
new file mode 100644
index 0000000..72043b7
--- /dev/null
+++ b/env/pt/pcr.h
@@ -0,0 +1,93 @@
+#ifndef _RISCV_PCR_H
+#define _RISCV_PCR_H
+
+#define SR_ET    0x00000001
+#define SR_EF    0x00000002
+#define SR_EV    0x00000004
+#define SR_EC    0x00000008
+#define SR_PS    0x00000010
+#define SR_S     0x00000020
+#define SR_U64   0x00000040
+#define SR_S64   0x00000080
+#define SR_VM    0x00000100
+#define SR_IM    0x00FF0000
+#define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
+#define SR_IM_SHIFT 16
+
+#define PCR_SR       0
+#define PCR_EPC      1
+#define PCR_BADVADDR 2
+#define PCR_EVEC     3
+#define PCR_COUNT    4
+#define PCR_COMPARE  5
+#define PCR_CAUSE    6
+#define PCR_PTBR     7
+#define PCR_SEND_IPI 8
+#define PCR_CLR_IPI  9
+#define PCR_COREID   10
+#define PCR_IMPL     11
+#define PCR_K0       12
+#define PCR_K1       13
+#define PCR_VECBANK  18
+#define PCR_VECCFG   19
+#define PCR_RESET    29
+#define PCR_TOHOST   30
+#define PCR_FROMHOST 31
+
+#define IMPL_ISASIM 1
+#define IMPL_ROCKET 2
+
+#define IRQ_IPI   5
+#define IRQ_TIMER 7
+
+#define CAUSE_MISALIGNED_FETCH 0
+#define CAUSE_FAULT_FETCH 1
+#define CAUSE_ILLEGAL_INSTRUCTION 2
+#define CAUSE_PRIVILEGED_INSTRUCTION 3
+#define CAUSE_FP_DISABLED 4
+#define CAUSE_SYSCALL 6
+#define CAUSE_BREAKPOINT 7
+#define CAUSE_MISALIGNED_LOAD 8
+#define CAUSE_MISALIGNED_STORE 9
+#define CAUSE_FAULT_LOAD 10
+#define CAUSE_FAULT_STORE 11
+#define CAUSE_VECTOR_DISABLED 12
+#define CAUSE_VECTOR_BANK 13
+
+#define CAUSE_VECTOR_MISALIGNED_FETCH 24
+#define CAUSE_VECTOR_FAULT_FETCH 25
+#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
+#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
+#define CAUSE_VECTOR_MISALIGNED_LOAD 28
+#define CAUSE_VECTOR_MISALIGNED_STORE 29
+#define CAUSE_VECTOR_FAULT_LOAD 30
+#define CAUSE_VECTOR_FAULT_STORE 31
+
+#ifdef __riscv
+
+#define ASM_CR(r)   _ASM_CR(r)
+#define _ASM_CR(r)  cr##r
+
+#ifndef __ASSEMBLER__
+
+#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
+          asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
+          __tmp2; })
+
+#define mfpcr(reg) ({ long __tmp; \
+          asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
+          __tmp; })
+
+#define setpcr(reg,val) ({ long __tmp; \
+          asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+          __tmp; })
+
+#define clearpcr(reg,val) ({ long __tmp; \
+          asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+          __tmp; })
+
+#endif
+
+#endif
+
+#endif
diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h
new file mode 100644
index 0000000..4c42803
--- /dev/null
+++ b/env/pt/riscv_test.h
@@ -0,0 +1,236 @@
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
+#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
+
+#include "pcr.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U                                                    \
+
+#define RVTEST_FP_ENABLE                                                \
+  setpcr cr0, 2;                                                        \
+  mfpcr a0, cr0;                                                        \
+  and   a0, a0, 2;                                                      \
+  beqz  a0, 1f;                                                         \
+  mtfsr x0;                                                             \
+1:
+
+#define RVTEST_PASS_NOFP                                                \
+  RVTEST_FP_ENABLE                                                      \
+  bnez a0, 2f;                                                          \
+  RVTEST_PASS                                                           \
+2:                                                                      \
+
+#define RVTEST_VEC_ENABLE                                               \
+  mfpcr a0, cr0;                                                        \
+  ori   a0, a0, 4;                                                      \
+  mtpcr a0, cr0;                                                        \
+  li    a0, 0xff;                                                       \
+  mtpcr a0, cr18;                                                       \
+
+#define RVTEST_CODE_BEGIN                                               \
+        .text;                                                          \
+        .align  4;                                                      \
+        .global _start;                                                 \
+_start:                                                                 \
+        RVTEST_FP_ENABLE                                                \
+        RVTEST_VEC_ENABLE                                               \
+        mfpcr a0, cr10; 1: bnez a0, 1b;                                 \
+        ENABLE_TIMER_INTERRUPT                                          \
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END                                                 \
+        XCPT_HANDLER                                                    \
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS                                                     \
+        fence;                                                          \
+        li  x1, 1;                                                      \
+        mtpcr x1, cr30;                                                 \
+1:      b 1b;                                                           \
+
+#define RVTEST_FAIL                                                     \
+        fence;                                                          \
+        beqz x28, 1f;                                                   \
+        sll x28, x28, 1;                                                \
+        or x28, x28, 1;                                                 \
+        mtpcr x28, cr30;                                                \
+1:      b 1b;                                                           \
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_DATA_BEGIN                                               \
+        .align 3; \
+regspill:                          \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+evac:                              \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+        .dword 0xdeadbeefcafebabe; \
+
+#define RVTEST_DATA_END
+
+//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
+//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+
+//-----------------------------------------------------------------------
+// Misc
+//-----------------------------------------------------------------------
+
+#define ENABLE_TIMER_INTERRUPT \
+        mtpcr x0,ASM_CR(PCR_CLR_IPI);\
+        mfpcr a0,ASM_CR(PCR_SR);     \
+        li a1, SR_ET|SR_IM;          \
+        or a0,a0,a1;                 \
+        mtpcr a0,ASM_CR(PCR_SR);     \
+        la a0,handler;               \
+        mtpcr a0,ASM_CR(PCR_EVEC);   \
+        mtpcr x0,ASM_CR(PCR_COUNT);  \
+        addi a0,x0,60;               \
+        mtpcr a0,ASM_CR(PCR_COMPARE);\
+
+#define XCPT_HANDLER \
+handler: \
+        mtpcr a0,ASM_CR(PCR_K0);     \
+        mtpcr a1,ASM_CR(PCR_K1);     \
+        la a0,regspill;              \
+        sd a2,0(a0);                 \
+        sd a3,8(a0);                 \
+        sd a4,16(a0);                \
+        sd a5,24(a0);                \
+        sd s0,32(a0);                \
+        sd s1,40(a0);                \
+        mfpcr s1,ASM_CR(PCR_VECBANK);\
+        mfpcr s0,ASM_CR(PCR_VECCFG); \
+        la a0,evac;                  \
+        vxcptevac a0;                \
+        mtpcr s1,ASM_CR(PCR_VECBANK);\
+        srli a1,s0,12;               \
+        andi a1,a1,0x3f;             \
+        srli a2,s0,18;               \
+        andi a2,a2,0x3f;             \
+        vvcfg a1,a2;                 \
+        li a2,0xfff;                 \
+        and a1,s0,a2;                \
+        vsetvl a1,a1;                \
+        vxcpthold;                   \
+        li a5,0;                     \
+handler_loop: \
+        ld a1,0(a0);                 \
+        addi a0,a0,8;                \
+        blt a1,x0,done;              \
+        srli a2,a1,32;               \
+        andi a2,a2,0x1;              \
+        beq a2,x0,vcnt;              \
+vcmd: \
+        beq a5,x0,vcmd_skip;         \
+        venqcmd a4,a3;               \
+vcmd_skip: \
+        li a5,1;                     \
+        move a4,a1;                  \
+        srli a3,a4,36;               \
+        andi a3,a3,0x1;              \
+vimm1: \
+        srli a2,a4,35;               \
+        andi a2,a2,0x1;              \
+        beq a2,x0,vimm2;             \
+        ld a1,0(a0);                 \
+        addi a0,a0,8;                \
+        venqimm1 a1,a3;              \
+vimm2: \
+        srli a2,a4,34;               \
+        andi a2,a2,0x1;              \
+        beq a2,x0,end;               \
+        ld a1,0(a0);                 \
+        addi a0,a0,8;                \
+        venqimm2 a1,a3;              \
+        j end;                       \
+vcnt: \
+        ld a2,0(a0);                 \
+        srli a2,a2,31;               \
+        andi a2,a2,0x2;              \
+        or a3,a3,a2;                 \
+        venqcnt a1,a3;               \
+end: \
+        j handler_loop;              \
+done: \
+        beq a5,x0,done_skip;         \
+        venqcmd a4,a3;               \
+done_skip: \
+        la a0,regspill;              \
+        ld a2,0(a0);                 \
+        ld a3,8(a0);                 \
+        ld a4,16(a0);                \
+        ld a5,24(a0);                \
+        ld s0,32(a0);                \
+        ld s1,40(a0);                \
+        mfpcr a0,ASM_CR(PCR_COUNT);  \
+        addi a0,a0,60;               \
+        mtpcr a0,ASM_CR(PCR_COMPARE);\
+        mfpcr a0,ASM_CR(PCR_K0);     \
+        mfpcr a1,ASM_CR(PCR_K1);     \
+        eret;                        \
+
+#endif
diff --git a/env/v/entry.S b/env/v/entry.S
new file mode 100644
index 0000000..35eaae3
--- /dev/null
+++ b/env/v/entry.S
@@ -0,0 +1,171 @@
+#include "riscv_test.h"
+
+#ifdef __riscv64
+# define STORE    sd
+# define LOAD     ld
+# define REGBYTES 8
+#else
+# define STORE    sw
+# define LOAD     lw
+# define REGBYTES 4
+#endif
+
+  .text
+  .global _start
+_start:
+  la sp, stack_top
+  li a1, 1337
+  la a0, userstart
+  j vm_boot
+
+save_tf:  # write the trap frame onto the stack
+
+  # save gprs
+  STORE  x3,3*REGBYTES(x2)
+  STORE  x4,4*REGBYTES(x2)
+  STORE  x5,5*REGBYTES(x2)
+  STORE  x6,6*REGBYTES(x2)
+  STORE  x7,7*REGBYTES(x2)
+  STORE  x8,8*REGBYTES(x2)
+  STORE  x9,9*REGBYTES(x2)
+  STORE  x10,10*REGBYTES(x2)
+  STORE  x11,11*REGBYTES(x2)
+  STORE  x12,12*REGBYTES(x2)
+  STORE  x13,13*REGBYTES(x2)
+  STORE  x14,14*REGBYTES(x2)
+  STORE  x15,15*REGBYTES(x2)
+  STORE  x16,16*REGBYTES(x2)
+  STORE  x17,17*REGBYTES(x2)
+  STORE  x18,18*REGBYTES(x2)
+  STORE  x19,19*REGBYTES(x2)
+  STORE  x20,20*REGBYTES(x2)
+  STORE  x21,21*REGBYTES(x2)
+  STORE  x22,22*REGBYTES(x2)
+  STORE  x23,23*REGBYTES(x2)
+  STORE  x24,24*REGBYTES(x2)
+  STORE  x25,25*REGBYTES(x2)
+  STORE  x26,26*REGBYTES(x2)
+  STORE  x27,27*REGBYTES(x2)
+  STORE  x28,28*REGBYTES(x2)
+  STORE  x29,29*REGBYTES(x2)
+  STORE  x30,30*REGBYTES(x2)
+  STORE  x31,31*REGBYTES(x2)
+
+  mfpcr  x3,ASM_CR(PCR_K0)
+  STORE  x3,1*REGBYTES(x2)          # x1 is in PCR_K0
+  mfpcr  x3,ASM_CR(PCR_K1)
+  STORE  x3,2*REGBYTES(x2)          # x2 is in PCR_K1
+
+  # get sr, epc, badvaddr, cause
+  mfpcr  x3,ASM_CR(PCR_SR)          # sr
+  STORE  x3,32*REGBYTES(x2)
+  mfpcr  x4,ASM_CR(PCR_EPC)          # epc
+  STORE  x4,33*REGBYTES(x2)
+  mfpcr  x3,ASM_CR(PCR_BADVADDR)      # badvaddr
+  STORE  x3,34*REGBYTES(x2)
+  mfpcr  x3,ASM_CR(PCR_CAUSE)        # cause
+  STORE  x3,35*REGBYTES(x2)
+
+  # get faulting insn, if it wasn't a fetch-related trap
+  li    x5, CAUSE_MISALIGNED_FETCH
+  li    x6, CAUSE_FAULT_FETCH
+  beq   x3, x5, 1f
+  beq   x3, x6, 1f
+  lh    x3,0(x4)
+  lh    x4,2(x4)
+  sh    x3,  36*REGBYTES(x2)
+  sh    x4,2+36*REGBYTES(x2)
+1:
+
+  mfpcr  x3,ASM_CR(PCR_VECBANK)        # vecbank
+  STORE  x3,37*REGBYTES(x2)
+  mfpcr  x3,ASM_CR(PCR_VECCFG)        # veccfg
+  STORE  x3,38*REGBYTES(x2)
+
+  ret
+
+  .globl  pop_tf
+pop_tf:  # write the trap frame onto the stack
+  # restore gprs
+  LOAD  a1,32*REGBYTES(a0)  # restore sr (should disable interrupts)
+  mtpcr  a1,ASM_CR(PCR_SR)
+
+  LOAD  x1,1*REGBYTES(a0)
+  mtpcr  x1,ASM_CR(PCR_K0)
+  LOAD  x1,2*REGBYTES(a0)
+  mtpcr x1,ASM_CR(PCR_K1)
+  move  x1,a0
+  LOAD  x3,3*REGBYTES(x1)
+  LOAD  x4,4*REGBYTES(x1)
+  LOAD  x5,5*REGBYTES(x1)
+  LOAD  x6,6*REGBYTES(x1)
+  LOAD  x7,7*REGBYTES(x1)
+  LOAD  x8,8*REGBYTES(x1)
+  LOAD  x9,9*REGBYTES(x1)
+  LOAD  x10,10*REGBYTES(x1)
+  LOAD  x11,11*REGBYTES(x1)
+  LOAD  x12,12*REGBYTES(x1)
+  LOAD  x13,13*REGBYTES(x1)
+  LOAD  x14,14*REGBYTES(x1)
+  LOAD  x15,15*REGBYTES(x1)
+  LOAD  x16,16*REGBYTES(x1)
+  LOAD  x17,17*REGBYTES(x1)
+  LOAD  x18,18*REGBYTES(x1)
+  LOAD  x19,19*REGBYTES(x1)
+  LOAD  x20,20*REGBYTES(x1)
+  LOAD  x21,21*REGBYTES(x1)
+  LOAD  x22,22*REGBYTES(x1)
+  LOAD  x23,23*REGBYTES(x1)
+  LOAD  x24,24*REGBYTES(x1)
+  LOAD  x25,25*REGBYTES(x1)
+  LOAD  x26,26*REGBYTES(x1)
+  LOAD  x27,27*REGBYTES(x1)
+  LOAD  x28,28*REGBYTES(x1)
+  LOAD  x29,29*REGBYTES(x1)
+  LOAD  x30,30*REGBYTES(x1)
+  LOAD  x31,31*REGBYTES(x1)
+
+  # gtfo!
+  LOAD  x2,33*REGBYTES(x1)
+  mtpcr x2,ASM_CR(PCR_EPC)
+  mfpcr x1,ASM_CR(PCR_K0)
+  mfpcr x2,ASM_CR(PCR_K1)
+  eret
+
+  .global  trap_entry
+trap_entry:
+  mtpcr ra,ASM_CR(PCR_K0)
+  mtpcr x2,ASM_CR(PCR_K1)
+
+  # coming from kernel?
+  mfpcr ra,ASM_CR(PCR_SR)
+  and   ra,ra,SR_PS
+  bnez  ra, 1f
+
+  # no, so start at the top of the stack
+  la    x2,stack_top+MAX_TEST_PAGES*PGSIZE-SIZEOF_TRAPFRAME_T
+  jal   save_tf
+  move  sp,x2
+  setpcr ASM_CR(PCR_SR), SR_ET
+  move  a0,x2
+  mfpcr ra,ASM_CR(PCR_SR)
+  and   ra,ra,SR_EV
+  beqz  ra, 2f
+  addi  x2,x2,39*REGBYTES
+  vxcptsave x2
+2:jal   handle_trap
+
+  # when coming from kernel, continue below its stack
+1:add   x2, sp, -SIZEOF_TRAPFRAME_T
+  jal   save_tf
+  move  sp,x2
+  setpcr ASM_CR(PCR_SR), SR_ET
+  move  a0,x2
+  jal   handle_trap
+
+  .bss
+  .global stack_bot
+  .global stack_top
+stack_bot:
+  .skip  32768
+stack_top:
diff --git a/env/v/link.ld b/env/v/link.ld
new file mode 100644
index 0000000..4efeaaa
--- /dev/null
+++ b/env/v/link.ld
@@ -0,0 +1,50 @@
+/*======================================================================*/
+/* Proxy kernel linker script                                           */
+/*======================================================================*/
+/* This is the linker script used when building the proxy kernel. */
+
+/*----------------------------------------------------------------------*/
+/* Setup                                                                */
+/*----------------------------------------------------------------------*/
+
+/* The OUTPUT_ARCH command specifies the machine architecture where the
+   argument is one of the names used in the BFD library. More
+   specifically one of the entires in bfd/cpu-mips.c */
+
+OUTPUT_ARCH( "riscv" )
+
+/* The ENTRY command specifies the entry point (ie. first instruction
+   to execute). The symbol _start should be defined in each test. */
+
+ENTRY( _start )
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+SECTIONS
+{
+
+  /* text: test code section */
+  . = 0x00002000;
+  .text :
+  {
+    *(.text)
+  }
+
+  /* data: Initialized data segment */
+  .data ALIGN(0x2000):
+  {
+    *(.data)
+  }
+
+  /* bss: Initialized bss segment */
+  .bss ALIGN(0x2000):
+  {
+    *(.bss)
+  }
+
+  /* End of uninitalized bss segement */
+  _end = .;
+}
+
diff --git a/env/v/pcr.h b/env/v/pcr.h
new file mode 100644
index 0000000..72043b7
--- /dev/null
+++ b/env/v/pcr.h
@@ -0,0 +1,93 @@
+#ifndef _RISCV_PCR_H
+#define _RISCV_PCR_H
+
+#define SR_ET    0x00000001
+#define SR_EF    0x00000002
+#define SR_EV    0x00000004
+#define SR_EC    0x00000008
+#define SR_PS    0x00000010
+#define SR_S     0x00000020
+#define SR_U64   0x00000040
+#define SR_S64   0x00000080
+#define SR_VM    0x00000100
+#define SR_IM    0x00FF0000
+#define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
+#define SR_IM_SHIFT 16
+
+#define PCR_SR       0
+#define PCR_EPC      1
+#define PCR_BADVADDR 2
+#define PCR_EVEC     3
+#define PCR_COUNT    4
+#define PCR_COMPARE  5
+#define PCR_CAUSE    6
+#define PCR_PTBR     7
+#define PCR_SEND_IPI 8
+#define PCR_CLR_IPI  9
+#define PCR_COREID   10
+#define PCR_IMPL     11
+#define PCR_K0       12
+#define PCR_K1       13
+#define PCR_VECBANK  18
+#define PCR_VECCFG   19
+#define PCR_RESET    29
+#define PCR_TOHOST   30
+#define PCR_FROMHOST 31
+
+#define IMPL_ISASIM 1
+#define IMPL_ROCKET 2
+
+#define IRQ_IPI   5
+#define IRQ_TIMER 7
+
+#define CAUSE_MISALIGNED_FETCH 0
+#define CAUSE_FAULT_FETCH 1
+#define CAUSE_ILLEGAL_INSTRUCTION 2
+#define CAUSE_PRIVILEGED_INSTRUCTION 3
+#define CAUSE_FP_DISABLED 4
+#define CAUSE_SYSCALL 6
+#define CAUSE_BREAKPOINT 7
+#define CAUSE_MISALIGNED_LOAD 8
+#define CAUSE_MISALIGNED_STORE 9
+#define CAUSE_FAULT_LOAD 10
+#define CAUSE_FAULT_STORE 11
+#define CAUSE_VECTOR_DISABLED 12
+#define CAUSE_VECTOR_BANK 13
+
+#define CAUSE_VECTOR_MISALIGNED_FETCH 24
+#define CAUSE_VECTOR_FAULT_FETCH 25
+#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
+#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
+#define CAUSE_VECTOR_MISALIGNED_LOAD 28
+#define CAUSE_VECTOR_MISALIGNED_STORE 29
+#define CAUSE_VECTOR_FAULT_LOAD 30
+#define CAUSE_VECTOR_FAULT_STORE 31
+
+#ifdef __riscv
+
+#define ASM_CR(r)   _ASM_CR(r)
+#define _ASM_CR(r)  cr##r
+
+#ifndef __ASSEMBLER__
+
+#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
+          asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
+          __tmp2; })
+
+#define mfpcr(reg) ({ long __tmp; \
+          asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
+          __tmp; })
+
+#define setpcr(reg,val) ({ long __tmp; \
+          asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+          __tmp; })
+
+#define clearpcr(reg,val) ({ long __tmp; \
+          asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+          __tmp; })
+
+#endif
+
+#endif
+
+#endif
diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h
new file mode 100644
index 0000000..4d9cceb
--- /dev/null
+++ b/env/v/riscv_test.h
@@ -0,0 +1,129 @@
+#ifndef _ENV_VIRTUAL_SINGLE_CORE_H
+#define _ENV_VIRTUAL_SINGLE_CORE_H
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U                                                    \
+
+#define RVTEST_RV64S                                                    \
+
+#define RVTEST_FP_ENABLE                                                \
+  mfpcr t0, cr0;                                                        \
+  or    t0, t0, 2;                                                      \
+  mtpcr t0, cr0;                                                        \
+  mtfsr x0;                                                             \
+
+#define RVTEST_VEC_ENABLE                                               \
+  mfpcr t0, cr0;                                                        \
+  ori   t0, t0, 4;                                                      \
+  mtpcr t0, cr0;                                                        \
+  li    t0, 0xff;                                                       \
+  mtpcr t0, cr11;                                                       \
+
+#define RVTEST_CODE_BEGIN                                               \
+        .text;                                                          \
+        .align  13;                                                     \
+        .global userstart;                                              \
+userstart:                                                              \
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END                                                 \
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS li a0, 1; syscall;
+#define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
+
+#define RVTEST_PASS_NOFP li a0, 1234; syscall;
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_DATA_BEGIN
+#define RVTEST_DATA_END
+
+//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
+//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+
+//-----------------------------------------------------------------------
+// Supervisor mode definitions and macros
+//-----------------------------------------------------------------------
+
+#include "pcr.h"
+
+#define vvcfg(nxregs, nfregs) ({ \
+          asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); })
+
+#define vsetvl(vl) ({ long __tmp; \
+          asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl)); })
+
+#define vcfg(word) ({ vvcfg((word)>>12, (word)>>18); vsetvl((word)); })
+
+#define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
+#define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
+#define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
+#define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
+#define dword_bit_pf(dw) ((dw >> 36) & 0x1)
+
+#define fencevl() ({ \
+          asm volatile ("fence.v.l" ::: "memory"); })
+
+#define vxcptkill() ({ \
+          asm volatile ("vxcptkill"); })
+
+#define vxcpthold() ({ \
+          asm volatile ("vxcpthold"); })
+
+#define venqcmd(bits, pf) ({ \
+          asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
+
+#define venqimm1(bits, pf) ({ \
+          asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
+
+#define venqimm2(bits, pf) ({ \
+          asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
+ 
+#define venqcnt(bits, pf) ({ \
+          asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
+
+#define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
+#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
+
+#define PGSHIFT 13
+#define PGSIZE (1 << PGSHIFT)
+
+#define SIZEOF_TRAPFRAME_T 1336
+
+#ifndef __ASSEMBLER__
+
+
+typedef unsigned long pte_t;
+#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
+#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
+#define VPN_BITS (PTIDXBITS * LEVELS)
+#define VA_BITS (VPN_BITS + PGSHIFT)
+#define PTES_PER_PT (PGSIZE/sizeof(pte_t))
+
+typedef struct
+{
+  long gpr[32];
+  long sr;
+  long epc;
+  long badvaddr;
+  long cause;
+  long insn;
+  long vecbank;
+  long veccfg;
+  long evac[128];
+} trapframe_t;
+#endif
+
+#endif
diff --git a/env/v/vm.c b/env/v/vm.c
new file mode 100644
index 0000000..37ef19e
--- /dev/null
+++ b/env/v/vm.c
@@ -0,0 +1,263 @@
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "riscv_test.h"
+
+void trap_entry();
+void pop_tf(trapframe_t*);
+
+static void cputchar(int x)
+{
+  while (mtpcr(PCR_TOHOST, 0x0101000000000000 | (unsigned char)x));
+}
+
+static void cputstring(const char* s)
+{
+  while(*s)
+    cputchar(*s++);
+  cputchar('\n');
+}
+
+static void terminate(int code)
+{
+  while (mtpcr(PCR_TOHOST, code));
+}
+
+#define stringify1(x) #x
+#define stringify(x) stringify1(x)
+#define assert(x) do { \
+  if (x) break; \
+  cputstring("Assertion failed: " stringify(x)); \
+  terminate(3); \
+  while(1); \
+} while(0)
+
+#define RELOC(x) ((typeof(x))((char*)(x) + (PGSIZE*MAX_TEST_PAGES)))
+
+typedef struct { pte_t addr; void* next; } freelist_t;
+
+pte_t l1pt[PTES_PER_PT] __attribute__((aligned(PGSIZE)));
+pte_t l2pt[PTES_PER_PT] __attribute__((aligned(PGSIZE)));
+pte_t l3pt[PTES_PER_PT] __attribute__((aligned(PGSIZE)));
+freelist_t user_mapping[MAX_TEST_PAGES];
+freelist_t freelist_nodes[MAX_TEST_PAGES];
+freelist_t *freelist_head, *freelist_tail;
+
+void printhex(uint64_t x)
+{
+  char str[17];
+  for (int i = 0; i < 16; i++)
+  {
+    str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
+    x >>= 4;
+  }
+  str[16] = 0;
+
+  cputstring(str);
+}
+
+void evict(unsigned long addr)
+{
+  assert(addr >= PGSIZE && addr < RELOC(0L));
+  addr = addr/PGSIZE*PGSIZE;
+
+  freelist_t* node = RELOC(&user_mapping[addr/PGSIZE]);
+  if (node->addr)
+  {
+    memcpy((void*)RELOC(addr), (void*)addr, PGSIZE);
+    RELOC(&user_mapping[addr/PGSIZE])->addr = 0;
+
+    if (*RELOC(&freelist_tail) == 0)
+      *RELOC(&freelist_head) = *RELOC(&freelist_tail) = node;
+    else
+    {
+      (*RELOC(&freelist_tail))->next = node;
+      *RELOC(&freelist_tail) = node;
+    }
+  }
+}
+
+void handle_fault(unsigned long addr)
+{
+  assert(addr >= PGSIZE && addr < RELOC(0L));
+  addr = addr/PGSIZE*PGSIZE;
+
+  freelist_t* node = *RELOC(&freelist_head);
+  assert(node);
+  *RELOC(&freelist_head) = node->next;
+  if (*RELOC(&freelist_head) == *RELOC(&freelist_tail))
+    *RELOC(&freelist_tail) = 0;
+
+  *RELOC(&l3pt[addr/PGSIZE]) = node->addr | 0x3F2;
+  mtpcr(PCR_PTBR, l1pt);
+
+  assert(RELOC(&user_mapping[addr/PGSIZE])->addr == 0);
+  *RELOC(&user_mapping[addr/PGSIZE]) = *node;
+  memcpy((void*)addr, (void*)RELOC(addr), PGSIZE);
+
+  __builtin___clear_cache(0,0);
+}
+
+void emulate_vxcptsave(trapframe_t* tf)
+{
+  long where = tf->gpr[(tf->insn >> 22) & 0x1F];
+
+  asm volatile ("vxcptevac %0" : : "r"(where));
+  fencevl();
+}
+
+void do_vxcptrestore(long* where)
+{
+  vxcpthold();
+
+  int idx = 0;
+  long dword, cmd, pf;
+  int first = 1;
+
+  while (1)
+  {
+    dword = where[idx++];
+
+    if (dword < 0) break;
+
+    if (dword_bit_cnt(dword))
+    {
+      venqcnt(dword, pf | (dword_bit_cmd(where[idx]) << 1));
+    }
+    else
+    {
+      if (!first)
+      {
+        venqcmd(cmd, pf);
+      }
+
+      first = 0;
+      cmd = dword;
+      pf = dword_bit_pf(cmd);
+
+      if (dword_bit_imm1(cmd))
+      {
+        venqimm1(where[idx++], pf);
+      }
+      if (dword_bit_imm2(cmd))
+      {
+        venqimm2(where[idx++], pf);
+      }
+    }
+  }
+  if (!first)
+  {
+    venqcmd(cmd, pf);
+  }
+}
+
+void emulate_vxcptrestore(trapframe_t* tf)
+{
+  long* where = (long*)tf->gpr[(tf->insn >> 22) & 0x1F];
+  vxcptkill();
+  vcfg(tf->veccfg);
+  do_vxcptrestore(where);
+}
+
+void restore_vector(trapframe_t* tf)
+{
+  mtpcr(PCR_VECBANK, tf->vecbank);
+  vcfg(tf->veccfg);
+
+  if (mfpcr(PCR_IMPL) == IMPL_ROCKET)
+    do_vxcptrestore(tf->evac);
+  else
+    asm volatile("vxcptrestore %0" : : "r"(tf->evac) : "memory");
+}
+
+void handle_trap(trapframe_t* tf)
+{
+  if (tf->cause == CAUSE_SYSCALL)
+  {
+    int n = tf->gpr[18];
+    if (n == 1234) // TEST_PASS_NOFP
+    {
+      if (mfpcr(PCR_SR) & SR_EF)
+      {
+        tf->epc += 4;
+        goto out;
+      }
+      n = 1;
+    }
+
+    for (long i = 1; i < MAX_TEST_PAGES; i++)
+      evict(i*PGSIZE);
+
+    terminate(n);
+    while(1);
+  }
+  else if (tf->cause == CAUSE_FAULT_FETCH)
+    handle_fault(tf->epc);
+  else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION)
+  {
+    if ((tf->insn & 0xF83FFFFF) == 0x37B)
+      emulate_vxcptsave(tf);
+    else if ((tf->insn & 0xF83FFFFF) == 0x77B)
+      emulate_vxcptrestore(tf);
+    else
+      assert(0);
+    tf->epc += 4;
+  }
+  else if (tf->cause == CAUSE_FAULT_LOAD || tf->cause == CAUSE_FAULT_STORE ||
+           tf->cause == CAUSE_VECTOR_FAULT_LOAD || tf->cause == CAUSE_VECTOR_FAULT_STORE ||
+           tf->cause == CAUSE_VECTOR_FAULT_FETCH)
+    handle_fault(tf->badvaddr);
+  else
+    assert(0);
+
+out:
+  if (!(tf->sr & SR_PS) && (tf->sr & SR_EV))
+    restore_vector(tf);
+  pop_tf(tf);
+}
+
+void vm_boot(long test_addr, long seed)
+{
+  while (mfpcr(PCR_COREID) > 0); // only core 0 proceeds
+
+  assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t));
+
+  seed = 1 + (seed % MAX_TEST_PAGES);
+  freelist_head = RELOC(&freelist_nodes[0]);
+  freelist_tail = RELOC(&freelist_nodes[MAX_TEST_PAGES-1]);
+  for (long i = 0; i < MAX_TEST_PAGES; i++)
+  {
+    freelist_nodes[i].addr = (MAX_TEST_PAGES+i)*PGSIZE;
+    freelist_nodes[i].next = RELOC(&freelist_nodes[i+1]);
+    seed = LFSR_NEXT(seed);
+  }
+  freelist_nodes[MAX_TEST_PAGES-1].next = 0;
+
+  assert(MAX_TEST_PAGES*2 < PTES_PER_PT);
+  l1pt[0] = (pte_t)l2pt | 1;
+  l2pt[0] = (pte_t)l3pt | 1;
+  for (long i = 0; i < MAX_TEST_PAGES; i++)
+    l3pt[i] = l3pt[i+MAX_TEST_PAGES] = (i*PGSIZE) | 0x382;
+
+  mtpcr(PCR_PTBR, l1pt);
+  mtpcr(PCR_SR, mfpcr(PCR_SR) | SR_VM | SR_EF);
+
+  if (mfpcr(PCR_SR) & SR_EF)
+    asm volatile ("mtfsr x0");
+
+  // relocate
+  long adjustment = RELOC(0L), tmp;
+  mtpcr(PCR_EVEC, (char*)&trap_entry + adjustment);
+  asm volatile ("add sp, sp, %1; rdpc %0; addi %0, %0, 16; add %0, %0, %1; jr %0" : "=&r"(tmp) : "r"(adjustment));
+
+  memset(RELOC(&l3pt[0]), 0, MAX_TEST_PAGES*sizeof(pte_t));
+  mtpcr(PCR_PTBR, l1pt);
+
+  trapframe_t tf;
+  memset(&tf, 0, sizeof(tf));
+  tf.sr = SR_EF | SR_EV | SR_S | SR_U64 | SR_S64 | SR_VM;
+  tf.epc = test_addr;
+
+  pop_tf(&tf);
+}
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
new file mode 100644
index 0000000..21ecdce
--- /dev/null
+++ b/isa/macros/scalar/test_macros.h
@@ -0,0 +1,690 @@
+#ifndef __TEST_MACROS_SCALAR_H
+#define __TEST_MACROS_SCALAR_H
+
+#define TEST_DATA
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    li  x29, correctval; \
+    li  x28, testnum; \
+    bne testreg, x29, fail;
+
+#define TEST_CASE_JUMP( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    li  x29, correctval; \
+    li  x28, testnum; \
+    beq testreg, x29, pass_ ## testnum; \
+    j fail; \
+pass_ ## testnum: \
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, val1; \
+      inst x3, x1, imm; \
+    )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1, imm; \
+    )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      inst x3, x1, imm; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      inst x3, x1, imm; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, imm; \
+    )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+    TEST_CASE( testnum, x0, 0, \
+      li  x1, val1; \
+      inst x0, x1, imm; \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for vector config instructions
+#-----------------------------------------------------------------------
+
+#define TEST_VVCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE_JUMP( testnum, x1, result, \
+      li x2, bank; \
+      mtpcr x2, cr18; \
+      li x1, vl; \
+      vvcfgivl x1,x1,nxpr,nfpr; \
+    )
+
+#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE_JUMP( testnum, x1, result, \
+      li x2, bank; \
+      mtpcr x2, cr18; \
+      li x1, nxpr; \
+      li x2, nfpr; \
+      vvcfg x1,x2; \
+      li x1, vl; \
+      vsetvl x1,x1; \
+    )
+
+#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE_JUMP( testnum, x1, result, \
+      li x2, bank; \
+      mtpcr x2, cr18; \
+      vvcfgivl x0,x0,nxpr,nfpr; \
+      li x1, vl; \
+      vsetvl x1, x1; \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, val1; \
+      inst x3, x1; \
+    )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1; \
+    )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      inst x3, x1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x3, x1, x2; \
+    )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x1, x1, x2; \
+    )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x2, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x2, x1, x2; \
+    )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1, x1; \
+    )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      li  x2, val2; \
+      inst x3, x1, x2; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x2, val2; \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x2, val2; \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x1, val1; \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, val; \
+      inst x2, x0, x1; \
+    )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, val; \
+      inst x2, x1, x0; \
+    )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+    TEST_CASE( testnum, x0, 0, \
+      li x1, val1; \
+      li x2, val2; \
+      inst x0, x1, x2; \
+    )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+    TEST_CASE( testnum, x3, result, \
+      la  x1, base; \
+      inst x3, offset(x1); \
+    )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+    TEST_CASE( testnum, x3, result, \
+      la  x1, base; \
+      li  x2, result; \
+      store_inst x2, offset(x1); \
+      load_inst x3, offset(x1); \
+    )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    inst x3, offset(x1); \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    addi  x6, x3, 0; \
+    li  x29, result; \
+    bne x6, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x3, offset(x1); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  la  x1, result; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    la  x2, base; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x3, offset(x2); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  la  x2, base; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    la  x1, result; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x3, offset(x2); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test branch instructions
+#-----------------------------------------------------------------------
+
+#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x1, val1; \
+    inst x1, 2f; \
+    bne x0, x28, fail; \
+1:  bne x0, x28, 3f; \
+2:  inst x1, 1b; \
+    bne x0, x28, fail; \
+3:
+
+#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x1, val1; \
+    inst x1, 1f; \
+    bne x0, x28, 2f; \
+1:  bne x0, x28, fail; \
+2:  inst x1, 1b; \
+3:
+
+#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x1, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 2f; \
+    bne x0, x28, fail; \
+1:  bne x0, x28, 3f; \
+2:  inst x1, x2, 1b; \
+    bne x0, x28, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 1f; \
+    bne x0, x28, 2f; \
+1:  bne x0, x28, fail; \
+2:  inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x6; \
+    bne x0, x28, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  x28, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x19, x6, 0; \
+    bne x0, x28, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define TEST_FP_OP_S_INTERNAL( testnum, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  x28, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  flw f0, 0(a0); \
+  flw f1, 4(a0); \
+  flw f2, 8(a0); \
+  lw  a3, 12(a0); \
+  code; \
+  bne a0, a3, fail; \
+  b 1f; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float val1; \
+  .float val2; \
+  .float val3; \
+  .result; \
+1:
+
+#define TEST_FP_OP_D_INTERNAL( testnum, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  x28, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  ld  a3, 24(a0); \
+  code; \
+  bne a0, a3, fail; \
+  b 1f; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+1:
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; mftx.d a0, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
+                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; mftx.s a0, f3)
+
+#define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
+                    inst f3, f0; mftx.s a0, f3)
+
+#define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; mftx.d a0, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, 0.0, \
+                    inst f3, f0, f1; mftx.s a0, f3)
+
+#define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; mftx.d a0, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; mftx.s a0, f3)
+
+#define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; mftx.d a0, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
+  TEST_FP_OP_S_INTERNAL( testnum, word result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_INT_OP_D( testnum, inst, result, val1, rm ) \
+  TEST_FP_OP_D_INTERNAL( testnum, dword result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, word result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  x28, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  mftx.s a0, f0; \
+  bne a0, a3, fail; \
+  b 1f; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float result; \
+1:
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  x28, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  ld  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  mftx.d a0, f0; \
+  bne a0, a3, fail; \
+  b 1f; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+1:
+
+#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
+  mfpcr a0,cr0; \
+  li a1,1; \
+  slli a3,a1,8; \
+  or a0,a0,a1; \
+  mtpcr a0,cr0; \
+  la a0, handler ## testnum; \
+  mtpcr a0, cr3; \
+  li a0, 4; \
+  vvcfgivl a0, a0, nxreg, nfreg; \
+  la a0, src1; \
+  la a1, src2; \
+  vld vx2, a0; \
+  vld vx3, a1; \
+  lui a0,%hi(vtcode1 ## testnum); \
+  vf %lo(vtcode1 ## testnum)(a0); \
+  la a3, dest; \
+  vsd vx2, a3; \
+  fence.v.l; \
+vtcode1 ## testnum: \
+  add x2, x2, x3; \
+illegal ## testnum: \
+  inst reg1, reg2, reg3; \
+  stop; \
+vtcode2 ## testnum: \
+  add x2, x2, x3; \
+  stop; \
+handler ## testnum: \
+  vxcptkill; \
+  li x28,2; \
+  mfpcr a0,cr6; \
+  li a1,26; \
+  bne a0,a1,fail; \
+  mfpcr a0,cr2; \
+  la a1,illegal ## testnum; \
+  bne a0,a1,fail; \
+  li a0,4; \
+  vvcfgivl a0,a0,32,0; \
+  la a0,src1; \
+  la a1,src2; \
+  vld vx2,a0; \
+  vld vx3,a1; \
+  lui a0,%hi(vtcode2 ## testnum); \
+  vf %lo(vtcode2 ## testnum)(a0); \
+  la a3,dest; \
+  vsd vx2,a3; \
+  fence.v.l; \
+  ld a1,0(a3); \
+  li a2,5; \
+  li x28,2; \
+  bne a1,a2,fail; \
+  ld a1,8(a3); \
+  li x28,3; \
+  bne a1,a2,fail; \
+  ld a1,16(a3); \
+  li x28,4; \
+  bne a1,a2,fail; \
+  ld a1,24(a3); \
+  li x28,5; \
+  bne a1,a2,fail; \
+
+#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, aux) \
+  mfpcr a0,cr0; \
+  li a1,1; \
+  slli a2,a1,8; \
+  or a0,a0,a1; \
+  mtpcr a0,cr0; \
+  la a0, handler ## testnum; \
+  mtpcr a0, cr3; \
+  li a0, 4; \
+  vvcfgivl a0, a0, nxreg, nfreg; \
+  la a0, src1; \
+  la a1, src2; \
+  vld vx2, a0; \
+  vld vx3, a1; \
+  lui a0,%hi(vtcode1 ## testnum); \
+  vf %lo(vtcode1 ## testnum)(a0); \
+  la reg2, dest; \
+illegal ## testnum: \
+  inst reg1, reg2; \
+  la a3, dest; \
+  vsd vx2, a3; \
+  fence.v.l; \
+vtcode1 ## testnum: \
+  add x2, x2, x3; \
+  stop; \
+vtcode2 ## testnum: \
+  add x2, x2, x3; \
+  stop; \
+handler ## testnum: \
+  vxcptkill; \
+  li x28,2; \
+  mfpcr a0,cr6; \
+  li a1,27; \
+  bne a0,a1,fail; \
+  mfpcr a0, cr2; \
+  li a1, aux; \
+  bne a0, a1, fail; \
+  li a0,4; \
+  vvcfgivl a0,a0,32,0; \
+  la a0,src1; \
+  la a1,src2; \
+  vld vx2,a0; \
+  vld vx3,a1; \
+  lui a0,%hi(vtcode2 ## testnum); \
+  vf %lo(vtcode2 ## testnum)(a0); \
+  la a3,dest; \
+  vsd vx2,a3; \
+  fence.v.l; \
+  ld a1,0(a3); \
+  li a2,5; \
+  li x28,2; \
+  bne a1,a2,fail; \
+  ld a1,8(a3); \
+  li x28,3; \
+  bne a1,a2,fail; \
+  ld a1,16(a3); \
+  li x28,4; \
+  bne a1,a2,fail; \
+  ld a1,24(a3); \
+  li x28,5; \
+  bne a1,a2,fail; \
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in x28)
+#-----------------------------------------------------------------------
+
+
+#define TEST_PASSFAIL \
+        bne x0, x28, pass; \
+fail: \
+        RVTEST_FAIL \
+pass: \
+        RVTEST_PASS \
+
+#endif
diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
new file mode 100644
index 0000000..a367291
--- /dev/null
+++ b/isa/macros/vector/test_macros.h
@@ -0,0 +1,584 @@
+#ifndef __TEST_MACROS_VECTOR_H
+#define __TEST_MACROS_VECTOR_H
+
+#define TEST_DATA \
+        .data; \
+        .align 3; \
+dst: \
+        .skip 16384; \
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+  TEST_CASE_NREG( testnum, 32, 32, testreg, correctval, code )
+
+# We use j fail, because for some cases branches are not enough to jump to fail
+
+#define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
+test_ ## testnum: \
+  li a3,2048; \
+  vvcfgivl a3,a3,nxreg,nfreg; \
+  lui a0,%hi(vtcode ## testnum ); \
+  vf %lo(vtcode ## testnum )(a0); \
+  la a4,dst; \
+  vsd v ## testreg, a4; \
+  fence.v.l; \
+  li a1,correctval; \
+  li a2,0; \
+  li x28, testnum; \
+test_loop ## testnum: \
+  ld a0,0(a4); \
+  beq a0,a1,skip ## testnum; \
+  j fail; \
+skip ## testnum : \
+  addi a4,a4,8; \
+  addi a2,a2,1; \
+  bne a2,a3,test_loop ## testnum; \
+  j next ## testnum; \
+vtcode ## testnum : \
+  code; \
+  stop; \
+next ## testnum :
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+    TEST_CASE_NREG( testnum, 4, 0, x3, result, \
+      li  x1, val1; \
+      inst x3, x1, imm; \
+    )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+    TEST_CASE_NREG( testnum, 2, 0, x1, result, \
+      li  x1, val1; \
+      inst x1, x1, imm; \
+    )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE_NREG( testnum, 5, 0, x4, result, \
+      li  x1, val1; \
+      inst x3, x1, imm; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x4, x3, 0; \
+    )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE_NREG( testnum, 4, 0, x3, result, \
+      li  x1, val1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      inst x3, x1, imm; \
+    )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+    TEST_CASE_NREG( testnum, 2, 0, x1, result, \
+      inst x1, x0, imm; \
+    )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+    TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
+      li  x1, val1; \
+      inst x0, x1, imm; \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+    TEST_CASE_NREG( testnum, 4, 0, x3, result, \
+      li  x1, val1; \
+      inst x3, x1; \
+    )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE_NREG( testnum, 2, 0, x1, result, \
+      li  x1, val1; \
+      inst x1, x1; \
+    )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+    TEST_CASE_NREG( testnum, 5, 0, x4, result, \
+      li  x1, val1; \
+      inst x3, x1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x4, x3, 0; \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+    TEST_CASE_NREG( testnum, 4, 0, x3, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x3, x1, x2; \
+    )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE_NREG( testnum, 3, 0, x1, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x1, x1, x2; \
+    )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE_NREG( testnum, 3, 0, x2, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x2, x1, x2; \
+    )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE_NREG( testnum, 2, 0, x1, result, \
+      li  x1, val1; \
+      inst x1, x1, x1; \
+    )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+    TEST_CASE_NREG( testnum, 5, 0, x4, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x3, x1, x2; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x4, x3, 0; \
+    )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE_NREG( testnum, 4, 0, x3, result, \
+      li  x1, val1; \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x2, val2; \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+    )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE_NREG( testnum, 4, 0, x3, result, \
+      li  x2, val2; \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x1, val1; \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+    )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+    TEST_CASE_NREG( testnum, 3, 0, x2, result, \
+      li x1, val; \
+      inst x2, x0, x1; \
+    )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+    TEST_CASE_NREG( testnum, 3, 0, x2, result, \
+      li x1, val; \
+      inst x2, x1, x0; \
+    )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+    TEST_CASE_NREG( testnum, 2, 0, x1, result, \
+      inst x1, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+    TEST_CASE_NREG( testnum, 3, 0, x0, 0, \
+      li x1, val1; \
+      li x2, val2; \
+      inst x0, x1, x2; \
+    )
+
+#-----------------------------------------------------------------------
+# Test branch instructions
+#-----------------------------------------------------------------------
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2) \
+    TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
+      li x1, val1; \
+      li x2, val2; \
+      add x3, x0, x0; \
+      inst x1, x2, 2f; \
+      addi x3, x3, 1; \
+1:    j 3f; \
+      addi x3, x3, 4; \
+2:    inst x1, x2, 1b; \
+      addi x3, x3, 2; \
+3: \
+    )
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+  TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
+    li  x1, val1; \
+    li  x2, val2; \
+    add x3, x0, x0; \
+    inst x1, x2, 1f; \
+    j 2f; \
+1:  addi x3, x3, 1; \
+    j 3f; \
+2:  inst x1, x2, 1b; \
+3: \
+                  )
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+  TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
+    add x3, x0, x0; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, 2f; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b; \
+    j 3f; \
+2:  add x3, x3, 1; \
+3:  \
+  )
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+  TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
+    add x3, x0, x0; \
+    li  x4, 0; \
+1:  li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, 2f; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x4, 1b; \
+    j 3f; \
+2:  add x3, x3, 1; \
+3: \
+                  )
+
+#define TEST_BR2_DIVERGED_ODD_EVEN( testnum, inst, n, result, code...)   \
+  TEST_CASE_NREG( testnum, 5, 0, x3, result, \
+    utidx x1; \
+    andi x2, x1, 1;\
+    add x3, x0, x0; \
+    li x4, n; \
+1: \
+    beq x0, x2, 2f; \
+    code; \
+    j 3f; \
+2: \
+    code; \
+3: \
+    addi x4, x4, -1; \
+    bne x4, x0, 1b; \
+                  )
+
+#define TEST_BR2_DIVERGED_FULL12( testnum, inst, n, result, code... )    \
+  TEST_CASE_NREG( testnum, 5, 0, x3, result, \
+    utidx x1; \
+    sltiu x2, x1, 1; \
+    add x3, x0, x0; \
+    li x4, n; \
+1: \
+    inst x2, x4, 2f; \
+    addi x1, x1, -1; \
+    sltiu x2, x1, 1; \
+    j 1b; \
+2: \
+    code; \
+                 )
+
+#define TEST_BR2_DIVERGED_FULL21( testnum, inst, n, result, code... )    \
+  TEST_CASE_NREG( testnum, 5, 0, x3, result, \
+    utidx x1; \
+    sltiu x2, x1, 1; \
+    add x3, x0, x0; \
+    li x4, n; \
+1: \
+    inst x4, x2, 2f; \
+    addi x1, x1, -1; \
+    sltiu x2, x1, 1; \
+    j 1b; \
+2: \
+    code; \
+                 )
+
+#define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
+test_ ## testnum: \
+  li a3,2048; \
+  vvcfgivl a3,a3,nxreg,nfreg; \
+  lui a0,%hi(vtcode ## testnum ); \
+  vf %lo(vtcode ## testnum )(a0); \
+  la a4,dst; \
+  fence.v.l; \
+  li a1,correctval; \
+  li a2,0; \
+  li x28, testnum; \
+test_loop ## testnum: \
+  ld a0,0(a4); \
+  beq a0,a1,skip ## testnum; \
+  j fail; \
+skip ## testnum : \
+  addi a4,a4,8; \
+  addi a2,a2,1; \
+  bne a2,a3,test_loop ## testnum; \
+  j next ## testnum; \
+vtcode ## testnum : \
+  code; \
+  stop; \
+next ## testnum :
+
+#define TEST_BR2_DIVERGED_MEM_FULL12( testnum, inst, n) \
+  TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
+    utidx x5; \
+    slli x5, x5, 3; \
+    la x6, dst; \
+    add x5, x5, x6; \
+    sd x0, 0(x5); \
+    utidx x1; \
+    sltiu x2, x1, 1; \
+    li x4, n; \
+1: \
+    inst x2, x4, 2f; \
+    addi x1, x1, -1; \
+    sltiu x2, x1, 1; \
+    j 1b; \
+2: \
+    ld x3, 0(x5); \
+    addi x3, x3, 1; \
+    sd x3, 0(x5); \
+                 )
+
+#define TEST_BR2_DIVERGED_MEM_FULL21( testnum, inst, n) \
+  TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
+    utidx x5; \
+    slli x5, x5, 3; \
+    la x6, dst; \
+    add x5, x5, x6; \
+    sd x0, 0(x5); \
+    utidx x1; \
+    sltiu x2, x1, 1; \
+    li x4, n; \
+1: \
+    inst x4, x2, 2f; \
+    addi x1, x1, -1; \
+    sltiu x2, x1, 1; \
+    j 1b; \
+2: \
+    ld x3, 0(x5); \
+    addi x3, x3, 1; \
+    sd x3, 0(x5); \
+                 )
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li a3,2048; \
+  vvcfgivl a3,a3,nxreg,nfreg; \
+  la  a5, test_ ## testnum ## _data ;\
+  vflstw vf0, a5, x0; \
+  addi a5,a5,4; \
+  vflstw vf1, a5, x0; \
+  addi a5,a5,4; \
+  vflstw vf2, a5, x0; \
+  addi a5,a5,4; \
+  lui a0,%hi(vtcode ## testnum ); \
+  vf %lo(vtcode ## testnum )(a0); \
+  la a4,dst; \
+  vsw vx1, a4; \
+  fence.v.l; \
+  lw  a1, 0(a5); \
+  li a2, 0; \
+  li x28, testnum; \
+test_loop ## testnum: \
+  lw a0,0(a4); \
+  beq a0,a1,skip ## testnum; \
+  j fail; \
+skip ## testnum : \
+  addi a4,a4,4; \
+  addi a2,a2,1; \
+  bne a2,a3,test_loop ## testnum; \
+  b 1f; \
+vtcode ## testnum : \
+  code; \
+  stop; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float val1; \
+  .float val2; \
+  .float val3; \
+  .result; \
+1:
+
+#define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li a3,2048; \
+  vvcfgivl a3,a3,nxreg,nfreg; \
+  la  a5, test_ ## testnum ## _data ;\
+  vflstd vf0, a5, x0; \
+  addi a5,a5,8; \
+  vflstd vf1, a5, x0; \
+  addi a5,a5,8; \
+  vflstd vf2, a5, x0; \
+  addi a5,a5,8; \
+  lui a0,%hi(vtcode ## testnum ); \
+  vf %lo(vtcode ## testnum )(a0); \
+  la a4,dst; \
+  vsd vx1, a4; \
+  fence.v.l; \
+  ld  a1, 0(a5); \
+  li a2, 0; \
+  li x28, testnum; \
+test_loop ## testnum: \
+  ld a0,0(a4); \
+  beq a0,a1,skip ## testnum; \
+  j fail; \
+skip ## testnum : \
+  addi a4,a4,8; \
+  addi a2,a2,1; \
+  bne a2,a3,test_loop ## testnum; \
+  b 1f; \
+vtcode ## testnum : \
+  code; \
+  stop; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+1:
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; mftx.d x1, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
+                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; mftx.s x1, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
+                    inst f3, f0, f1; mftx.s x1, f3)
+
+#define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; mftx.d x1, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
+  TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; mftx.s x1, f3)
+
+#define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
+  TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; mftx.d x1, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
+  TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
+                    inst x1, f0, rm)
+
+#define TEST_FP_INT_OP_D( testnum, inst, result, val1, rm ) \
+  TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, 0.0, 0.0, \
+                    inst x1, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, val2, 0.0, \
+                    inst x1, f0, f1)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, val2, 0.0, \
+                    inst x1, f0, f1)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li a3,2048; \
+  vvcfgivl a3,a3,2,1; \
+  lui a0,%hi(vtcode ## testnum ); \
+  vf %lo(vtcode ## testnum )(a0); \
+  la a4,dst; \
+  vsw vx1, a4; \
+  fence.v.l; \
+  la  a5, test_ ## testnum ## _data ;\
+  lw  a1, 0(a5); \
+  li a2, 0; \
+  li x28, testnum; \
+test_loop ## testnum: \
+  lw a0,0(a4); \
+  beq a0,a1,skip ## testnum; \
+  j fail; \
+skip ## testnum : \
+  addi a4,a4,4; \
+  addi a2,a2,1; \
+  bne a2,a3,test_loop ## testnum; \
+  b 1f; \
+vtcode ## testnum : \
+  li x1, val1; \
+  inst f0, x1; \
+  mftx.s x1, f0; \
+  stop; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float result; \
+1:
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li a3,2048; \
+  vvcfgivl a3,a3,2,1; \
+  lui a0,%hi(vtcode ## testnum ); \
+  vf %lo(vtcode ## testnum )(a0); \
+  la a4,dst; \
+  vsd vx1, a4; \
+  fence.v.l; \
+  la  a5, test_ ## testnum ## _data ;\
+  ld  a1, 0(a5); \
+  li a2, 0; \
+  li x28, testnum; \
+test_loop ## testnum: \
+  ld a0,0(a4); \
+  beq a0,a1,skip ## testnum; \
+  j fail; \
+skip ## testnum : \
+  addi a4,a4,8; \
+  addi a2,a2,1; \
+  bne a2,a3,test_loop ## testnum; \
+  b 1f; \
+vtcode ## testnum : \
+  li x1, val1; \
+  inst f0, x1; \
+  mftx.d x1, f0; \
+  stop; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+1:
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in x28)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+        bne x0, x28, pass; \
+fail: \
+        RVTEST_FAIL \
+pass: \
+        RVTEST_PASS \
+
+#endif
diff --git a/isa/rv64si/Makefile b/isa/rv64si/Makefile
new file mode 100644
index 0000000..c6db077
--- /dev/null
+++ b/isa/rv64si/Makefile
@@ -0,0 +1,99 @@
+#=======================================================================
+# Makefile for riscv-tests
+#-----------------------------------------------------------------------
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+rv64si_sc_tests = \
+	coreid \
+
+rv64si_mc_tests = \
+	ipi \
+
+rv64si_sc_vec_tests = \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss
+RISCV_SIM = riscv-isa-run
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.hex: %
+	elf2hex 16 16384 $< > $@
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) $< 2> $@
+
+rv64si_p_tests_bin = $(addprefix rv64si-p-, $(rv64si_sc_tests))
+rv64si_p_tests_dump = $(addsuffix .dump, $(rv64si_p_tests_bin))
+rv64si_p_tests_hex = $(addsuffix .hex, $(rv64si_p_tests_bin))
+rv64si_p_tests_out  = $(addsuffix .out,  $(rv64si_p_tests_bin))
+
+$(rv64si_p_tests_bin): rv64si-p-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/scalar -T../../env/p/link.ld $< -o $@
+
+rv64si_pm_tests_bin = $(addprefix rv64si-pm-, $(rv64si_mc_tests))
+rv64si_pm_tests_dump = $(addsuffix .dump, $(rv64si_pm_tests_bin))
+rv64si_pm_tests_hex = $(addsuffix .hex, $(rv64si_pm_tests_bin))
+rv64si_pm_tests_out  = $(addsuffix .out,  $(rv64si_pm_tests_bin))
+
+$(rv64si_pm_tests_bin): rv64si-pm-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pm -I../macros/scalar -T../../env/pm/link.ld $< -o $@
+
+rv64si_p_vec_tests_bin = $(addprefix rv64si-p-vec-, $(rv64si_sc_vec_tests))
+rv64si_p_vec_tests_dump = $(addsuffix .dump, $(rv64si_p_vec_tests_bin))
+rv64si_p_vec_tests_hex = $(addsuffix .hex, $(rv64si_p_vec_tests_bin))
+rv64si_p_vec_tests_out  = $(addsuffix .out,  $(rv64si_p_vec_tests_bin))
+
+$(rv64si_p_vec_tests_bin): rv64si-p-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/vector -T../../env/p/link.ld $< -o $@
+
+rv64si_pt_vec_tests_bin = $(addprefix rv64si-pt-vec-, $(rv64si_sc_vec_tests))
+rv64si_pt_vec_tests_dump = $(addsuffix .dump, $(rv64si_pt_vec_tests_bin))
+rv64si_pt_vec_tests_hex = $(addsuffix .hex, $(rv64si_pt_vec_tests_bin))
+rv64si_pt_vec_tests_out  = $(addsuffix .out,  $(rv64si_pt_vec_tests_bin))
+
+$(rv64si_pt_vec_tests_bin): rv64si-pt-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pt -I../macros/vector -T../../env/pt/link.ld $< -o $@
+
+riscv-: \
+	$(rv64si_p_tests_dump) $(rv64si_p_tests_hex) \
+	$(rv64si_pm_tests_dump) $(rv64si_pm_tests_hex) \
+	$(rv64si_p_vec_tests_dump) $(rv64si_p_vec_tests_hex) \
+	$(rv64si_pt_vec_tests_dump) $(rv64si_pt_vec_tests_hex) \
+
+out = $(rv64si_p_tests_out) $(rv64si_pm_tests_out) $(rv64si_p_vec_tests_out)
+
+run: $(out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(out); echo;
+
+junk += \
+  $(rv64si_p_tests_bin) $(rv64si_p_tests_dump) $(rv64si_p_tests_hex) $(rv64si_p_tests_out) \
+  $(rv64si_pm_tests_bin) $(rv64si_pm_tests_dump) $(rv64si_pm_tests_hex) $(rv64si_pm_tests_out) \
+  $(rv64si_p_vec_tests_bin) $(rv64si_p_vec_tests_dump) $(rv64si_p_vec_tests_hex) $(rv64si_p_vec_tests_out) \
+  $(rv64si_pt_vec_tests_bin) $(rv64si_pt_vec_tests_dump) $(rv64si_pt_vec_tests_hex) $(rv64si_pt_vec_tests_out) \
+
+#------------------------------------------------------------
+# Default
+
+all: riscv-
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/isa/rv64si/coreid.S b/isa/rv64si/coreid.S
new file mode 100644
index 0000000..2b7ffc3
--- /dev/null
+++ b/isa/rv64si/coreid.S
@@ -0,0 +1,29 @@
+#*****************************************************************************
+# coreid.S
+#-----------------------------------------------------------------------------
+#
+# Test coreid.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_CASE( 2, x1, 0x0, mfpcr x1, cr12 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S
new file mode 100644
index 0000000..92ae149
--- /dev/null
+++ b/isa/rv64si/ipi.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# ipi.S
+#-----------------------------------------------------------------------------
+#
+# Test interprocessor interrupts.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  # clear pending IPIs then enable interrupts
+  la a0, handler
+  mtpcr a0, cr3
+  mtpcr x0, cr9
+  mfpcr a0, cr0
+  li a1, 0x00ff0001
+  or a0, a0, a1
+  mtpcr a0, cr0
+
+  # wait for all cores to boot
+  la a0, coreid
+  li a1, 1
+  amoadd.w x0, a1, 0(a0)
+  lw a3, 4(x0)
+  1: lw a1, 0(a0)
+  blt a1, a3, 1b
+
+  # IPI dominoes
+  mfpcr a0, cr10
+  1: bnez a0, 1b
+  add a0, a0, 1
+  rem a0, a0, a3
+  mtpcr a0, cr8
+  1: b 1b
+
+  handler:
+  mfpcr a0, cr10
+  bnez a0, 2f
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  2: add a0, a0, 1
+  rem a0, a0, a3
+  mtpcr a0, cr8
+  1: b 1b
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+coreid: .word 0
+foo: .word 0
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/Makefile b/isa/rv64sv/Makefile
new file mode 100644
index 0000000..670f8d9
--- /dev/null
+++ b/isa/rv64sv/Makefile
@@ -0,0 +1,101 @@
+#=======================================================================
+# Makefile for riscv-tests
+#-----------------------------------------------------------------------
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+rv64sv_sc_tests = \
+	illegal_tvec_cmd illegal_tvec_regid \
+	illegal_vt_inst illegal_vt_regid \
+	ma_utld ma_utsd ma_vld ma_vsd \
+	ma_vt_inst \
+
+rv64sv_mc_tests = \
+
+rv64sv_sc_vec_tests = \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss
+RISCV_SIM = riscv-isa-run
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.hex: %
+	elf2hex 16 16384 $< > $@
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) $< 2> $@
+
+rv64sv_p_tests_bin = $(addprefix rv64sv-p-, $(rv64sv_sc_tests))
+rv64sv_p_tests_dump = $(addsuffix .dump, $(rv64sv_p_tests_bin))
+rv64sv_p_tests_hex = $(addsuffix .hex, $(rv64sv_p_tests_bin))
+rv64sv_p_tests_out  = $(addsuffix .out,  $(rv64sv_p_tests_bin))
+
+$(rv64sv_p_tests_bin): rv64sv-p-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/scalar -T../../env/p/link.ld $< -o $@
+
+rv64sv_pm_tests_bin = $(addprefix rv64sv-pm-, $(rv64sv_mc_tests))
+rv64sv_pm_tests_dump = $(addsuffix .dump, $(rv64sv_pm_tests_bin))
+rv64sv_pm_tests_hex = $(addsuffix .hex, $(rv64sv_pm_tests_bin))
+rv64sv_pm_tests_out  = $(addsuffix .out,  $(rv64sv_pm_tests_bin))
+
+$(rv64sv_pm_tests_bin): rv64sv-pm-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pm -I../macros/scalar -T../../env/pm/link.ld $< -o $@
+
+rv64sv_p_vec_tests_bin = $(addprefix rv64sv-p-vec-, $(rv64sv_sc_vec_tests))
+rv64sv_p_vec_tests_dump = $(addsuffix .dump, $(rv64sv_p_vec_tests_bin))
+rv64sv_p_vec_tests_hex = $(addsuffix .hex, $(rv64sv_p_vec_tests_bin))
+rv64sv_p_vec_tests_out  = $(addsuffix .out,  $(rv64sv_p_vec_tests_bin))
+
+$(rv64sv_p_vec_tests_bin): rv64sv-p-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/vector -T../../env/p/link.ld $< -o $@
+
+rv64sv_pt_vec_tests_bin = $(addprefix rv64sv-pt-vec-, $(rv64sv_sc_vec_tests))
+rv64sv_pt_vec_tests_dump = $(addsuffix .dump, $(rv64sv_pt_vec_tests_bin))
+rv64sv_pt_vec_tests_hex = $(addsuffix .hex, $(rv64sv_pt_vec_tests_bin))
+rv64sv_pt_vec_tests_out  = $(addsuffix .out,  $(rv64sv_pt_vec_tests_bin))
+
+$(rv64sv_pt_vec_tests_bin): rv64sv-pt-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pt -I../macros/vector -T../../env/pt/link.ld $< -o $@
+
+riscv-: \
+	$(rv64sv_p_tests_dump) $(rv64sv_p_tests_hex) \
+	$(rv64sv_pm_tests_dump) $(rv64sv_pm_tests_hex) \
+	$(rv64sv_p_vec_tests_dump) $(rv64sv_p_vec_tests_hex) \
+	$(rv64sv_pt_vec_tests_dump) $(rv64sv_pt_vec_tests_hex) \
+
+out =
+
+run: $(out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(out); echo;
+
+junk += \
+  $(rv64sv_p_tests_bin) $(rv64sv_p_tests_dump) $(rv64sv_p_tests_hex) $(rv64sv_p_tests_out) \
+  $(rv64sv_pm_tests_bin) $(rv64sv_pm_tests_dump) $(rv64sv_pm_tests_hex) $(rv64sv_pm_tests_out) \
+  $(rv64sv_p_vec_tests_bin) $(rv64sv_p_vec_tests_dump) $(rv64sv_p_vec_tests_hex) $(rv64sv_p_vec_tests_out) \
+  $(rv64sv_pt_vec_tests_bin) $(rv64sv_pt_vec_tests_dump) $(rv64sv_pt_vec_tests_hex) $(rv64sv_pt_vec_tests_out) \
+
+#------------------------------------------------------------
+# Default
+
+all: riscv-
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/isa/rv64sv/illegal_tvec_cmd.S b/isa/rv64sv/illegal_tvec_cmd.S
new file mode 100644
index 0000000..d6d8d38
--- /dev/null
+++ b/isa/rv64sv/illegal_tvec_cmd.S
@@ -0,0 +1,112 @@
+#*****************************************************************************
+# illegal_tvec_cmd.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal tvec command trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vmsv vx1, a3
+  addi a3, x0, 0x1
+  sll a3, a3, 12
+  venqcmd a3, x0
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  lw x2, 0(x1)
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,27
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  addi a4, x0, 0x1
+  sll a4, a4, 12
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
new file mode 100644
index 0000000..4f48f8f
--- /dev/null
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -0,0 +1,51 @@
+#*****************************************************************************
+# illegal_tvec_regid.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal tvec regid trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a0,cr0
+  li a1,1
+  slli a2,a1,8
+  or a0,a0,a1 # enable traps
+  mtpcr a0,cr0
+
+  TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2, 0x931c7)
+  TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2, 0x831c7)
+
+  TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2, 0x9b9e7)
+  TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2, 0x8b9e7)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
new file mode 100644
index 0000000..d749104
--- /dev/null
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -0,0 +1,112 @@
+#*****************************************************************************
+# illegal_vt_inst.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal vt instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  add x2,x2,x3
+illegal:
+  .word 0x0
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,26
+  bne a3,a4,fail
+
+  # check badvaddr
+  mfpcr a3,cr2
+  la a4,illegal
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
new file mode 100644
index 0000000..8baa918
--- /dev/null
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -0,0 +1,53 @@
+#*****************************************************************************
+# xcpt_illegal_vt_regid.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal vt regid trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a0,cr0
+  li a1,1
+  slli a2,a1,8
+  or a0,a0,a1 # enable traps
+  mtpcr a0,cr0
+
+  TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
+  TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)
+  TEST_ILLEGAL_VT_REGID(4, 5, 5, add, x1, x2, x7)
+
+  TEST_ILLEGAL_VT_REGID(5, 5, 5, fadd.d, f7, f1, f2)
+  TEST_ILLEGAL_VT_REGID(6, 5, 5, fadd.d, f1, f7, f2)
+  TEST_ILLEGAL_VT_REGID(7, 5, 5, fadd.d, f1, f2, f7)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
new file mode 100644
index 0000000..a71c4a1
--- /dev/null
+++ b/isa/rv64sv/ma_utld.S
@@ -0,0 +1,108 @@
+#*****************************************************************************
+# ma_utld.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ut ld trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vmsv vx1, a3
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  lw x2, 0(x1)
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,28
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4,dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
new file mode 100644
index 0000000..6bdfcd5
--- /dev/null
+++ b/isa/rv64sv/ma_utsd.S
@@ -0,0 +1,110 @@
+#*****************************************************************************
+# ma_utsd.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ut sd trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vmsv vx1, a3
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a3, dest+1
+  vsd vx1, a3
+  fence.v.l
+
+vtcode1:
+  sw x2, 0(x1)
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,29
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4, dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
new file mode 100644
index 0000000..ef862c4
--- /dev/null
+++ b/isa/rv64sv/ma_vld.S
@@ -0,0 +1,109 @@
+#*****************************************************************************
+# ma_vld.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned vector ld trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, dest+1
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  fence.v.l
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,28
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4,dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
new file mode 100644
index 0000000..b82eb98
--- /dev/null
+++ b/isa/rv64sv/ma_vsd.S
@@ -0,0 +1,112 @@
+#*****************************************************************************
+# ma_vsd.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned vector sd trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3, src1
+  la a4, src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a3, dest+1
+  vsd vx1, a3
+  fence.v.l
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+vtcode2:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,29
+  bne a3,a4,fail
+
+  # check vec irq aux
+  mfpcr a3,cr2
+  la a4,dest+1
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
new file mode 100644
index 0000000..c8b7acb
--- /dev/null
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -0,0 +1,102 @@
+#*****************************************************************************
+# ma_vt_inst.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned vt instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  mfpcr a3,cr0
+  li a4,1
+  slli a5,a4,8
+  or a3,a3,a4 # enable traps
+  mtpcr a3,cr0
+
+  la a3,handler
+  mtpcr a3,cr3 # set exception handler
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  lui a0,%hi(vtcode1+2)
+  vf %lo(vtcode1+2)(a0)
+1:      j 1b
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+handler:
+  vxcptkill
+
+  li x28,2
+
+  # check cause
+  mfpcr a3,cr6
+  li a4,24
+  bne a3,a4,fail
+
+  # check badvaddr
+  mfpcr a3,cr2
+  la a4,vtcode1+2
+  bne a3,a4,fail
+
+  # make sure vector unit has cleared out
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/Makefile b/isa/rv64uf/Makefile
new file mode 100644
index 0000000..65470ed
--- /dev/null
+++ b/isa/rv64uf/Makefile
@@ -0,0 +1,120 @@
+#=======================================================================
+# Makefile for riscv-tests
+#-----------------------------------------------------------------------
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+rv64uf_sc_tests = \
+	fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
+	ldst move structural \
+
+rv64uf_mc_tests =\
+
+rv64uf_sc_vec_tests = \
+	fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss
+RISCV_SIM = riscv-isa-run
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.hex: %
+	elf2hex 16 16384 $< > $@
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) $< 2> $@
+
+rv64uf_p_tests_bin = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
+rv64uf_p_tests_dump = $(addsuffix .dump, $(rv64uf_p_tests_bin))
+rv64uf_p_tests_hex = $(addsuffix .hex, $(rv64uf_p_tests_bin))
+rv64uf_p_tests_out  = $(addsuffix .out,  $(rv64uf_p_tests_bin))
+
+$(rv64uf_p_tests_bin): rv64uf-p-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/scalar -T../../env/p/link.ld $< -o $@
+
+rv64uf_pm_tests_bin = $(addprefix rv64uf-pm-, $(rv64uf_mc_tests))
+rv64uf_pm_tests_dump = $(addsuffix .dump, $(rv64uf_pm_tests_bin))
+rv64uf_pm_tests_hex = $(addsuffix .hex, $(rv64uf_pm_tests_bin))
+rv64uf_pm_tests_out  = $(addsuffix .out,  $(rv64uf_pm_tests_bin))
+
+$(rv64uf_pm_tests_bin): rv64uf-pm-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pm -I../macros/scalar -T../../env/pm/link.ld $< -o $@
+
+rv64uf_v_tests_bin = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
+rv64uf_v_tests_dump = $(addsuffix .dump, $(rv64uf_v_tests_bin))
+rv64uf_v_tests_hex = $(addsuffix .hex, $(rv64uf_v_tests_bin))
+rv64uf_v_tests_out  = $(addsuffix .out,  $(rv64uf_v_tests_bin))
+
+$(rv64uf_v_tests_bin): rv64uf-v-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -std=gnu99 -O2 -I../../env/v -I../macros/scalar -T../../env/v/link.ld ../../env/v/entry.S ../../env/v/vm.c $< -lc -o $@
+
+rv64uf_p_vec_tests_bin = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_p_vec_tests_dump = $(addsuffix .dump, $(rv64uf_p_vec_tests_bin))
+rv64uf_p_vec_tests_hex = $(addsuffix .hex, $(rv64uf_p_vec_tests_bin))
+rv64uf_p_vec_tests_out  = $(addsuffix .out,  $(rv64uf_p_vec_tests_bin))
+
+$(rv64uf_p_vec_tests_bin): rv64uf-p-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/vector -T../../env/p/link.ld $< -o $@
+
+rv64uf_pt_vec_tests_bin = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_pt_vec_tests_dump = $(addsuffix .dump, $(rv64uf_pt_vec_tests_bin))
+rv64uf_pt_vec_tests_hex = $(addsuffix .hex, $(rv64uf_pt_vec_tests_bin))
+rv64uf_pt_vec_tests_out  = $(addsuffix .out,  $(rv64uf_pt_vec_tests_bin))
+
+$(rv64uf_pt_vec_tests_bin): rv64uf-pt-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pt -I../macros/vector -T../../env/pt/link.ld $< -o $@
+
+rv64uf_v_vec_tests_bin = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_v_vec_tests_dump = $(addsuffix .dump, $(rv64uf_v_vec_tests_bin))
+rv64uf_v_vec_tests_hex = $(addsuffix .hex, $(rv64uf_v_vec_tests_bin))
+rv64uf_v_vec_tests_out  = $(addsuffix .out,  $(rv64uf_v_vec_tests_bin))
+
+$(rv64uf_v_vec_tests_bin): rv64uf-v-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -std=gnu99 -O2 -I../../env/v -I../macros/vector -T../../env/v/link.ld ../../env/v/entry.S ../../env/v/vm.c $< -lc -o $@
+
+riscv-: \
+	$(rv64uf_p_tests_dump) $(rv64uf_p_tests_hex) \
+	$(rv64uf_pm_tests_dump) $(rv64uf_pm_tests_hex) \
+	$(rv64uf_v_tests_dump) $(rv64uf_v_tests_hex) \
+	$(rv64uf_p_vec_tests_dump) $(rv64uf_p_vec_tests_hex) \
+	$(rv64uf_pt_vec_tests_dump) $(rv64uf_pt_vec_tests_hex) \
+	$(rv64uf_v_vec_tests_dump) $(rv64uf_v_vec_tests_hex) \
+
+out = $(rv64uf_p_tests_out) $(rv64uf_pm_tests_out) $(rv64uf_v_tests_out) $(rv64uf_p_vec_tests_out) $(rv64uf_v_vec_tests_out)
+
+run: $(out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(out); echo;
+
+junk += \
+  $(rv64uf_p_tests_bin) $(rv64uf_p_tests_dump) $(rv64uf_p_tests_hex) $(rv64uf_p_tests_out) \
+  $(rv64uf_pm_tests_bin) $(rv64uf_pm_tests_dump) $(rv64uf_pm_tests_hex) $(rv64uf_pm_tests_out) \
+  $(rv64uf_v_tests_bin) $(rv64uf_v_tests_dump) $(rv64uf_v_tests_hex) $(rv64uf_v_tests_out) \
+  $(rv64uf_p_vec_tests_bin) $(rv64uf_p_vec_tests_dump) $(rv64uf_p_vec_tests_hex) $(rv64uf_p_vec_tests_out) \
+  $(rv64uf_pt_vec_tests_bin) $(rv64uf_pt_vec_tests_dump) $(rv64uf_pt_vec_tests_hex) $(rv64uf_pt_vec_tests_out) \
+  $(rv64uf_v_vec_tests_bin) $(rv64uf_v_vec_tests_dump) $(rv64uf_v_vec_tests_hex) $(rv64uf_v_vec_tests_out) \
+
+#------------------------------------------------------------
+# Default
+
+all: riscv-
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/isa/rv64uf/fadd.S b/isa/rv64uf/fadd.S
new file mode 100644
index 0000000..58f44be
--- /dev/null
+++ b/isa/rv64uf/fadd.S
@@ -0,0 +1,51 @@
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.{s|d} instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_S( 2,  fadd.s,                3.5,        2.5,        1.0 );
+  TEST_FP_OP2_S( 3,  fadd.s,              -1234,    -1235.1,        1.1 );
+  TEST_FP_OP2_S( 4,  fadd.s,         3.14159265, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_D( 5,  fadd.d,                3.5,        2.5,        1.0 );
+  TEST_FP_OP2_D( 6,  fadd.d,              -1234,    -1235.1,        1.1 );
+  TEST_FP_OP2_D( 7,  fadd.d,         3.14159266, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_S(12,  fsub.s,                1.5,        2.5,        1.0 );
+  TEST_FP_OP2_S(13,  fsub.s,              -1234,    -1235.1,       -1.1 );
+  TEST_FP_OP2_S(14,  fsub.s,         3.14159265, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_D(15,  fsub.d,                1.5,        2.5,        1.0 );
+  TEST_FP_OP2_D(16,  fsub.d,              -1234,    -1235.1,       -1.1 );
+  TEST_FP_OP2_D(17,  fsub.d, 3.1415926400000001, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_S(22,  fmul.s,                2.5,        2.5,        1.0 );
+  TEST_FP_OP2_S(23,  fmul.s,            1358.61,    -1235.1,       -1.1 );
+  TEST_FP_OP2_S(24,  fmul.s,      3.14159265e-8, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_D(25,  fmul.d,                2.5,        2.5,        1.0 );
+  TEST_FP_OP2_D(26,  fmul.d,            1358.61,    -1235.1,       -1.1 );
+  TEST_FP_OP2_D(27,  fmul.d,      3.14159265e-8, 3.14159265, 0.00000001 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/fcmp.S b/isa/rv64uf/fcmp.S
new file mode 100644
index 0000000..845db3c
--- /dev/null
+++ b/isa/rv64uf/fcmp.S
@@ -0,0 +1,35 @@
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.{s|d} instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_CMP_OP_S( 2, feq.s, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_S( 3, fle.s, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_S( 4, flt.s, 0, -1.36, -1.36)
+
+  TEST_FP_CMP_OP_S( 5, feq.s, 0, -1.37, -1.36)
+  TEST_FP_CMP_OP_S( 6, fle.s, 1, -1.37, -1.36)
+  TEST_FP_CMP_OP_S( 7, flt.s, 1, -1.37, -1.36)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S
new file mode 100644
index 0000000..bb9a9c4
--- /dev/null
+++ b/isa/rv64uf/fcvt.S
@@ -0,0 +1,54 @@
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.{s|d}.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_INT_FP_OP_S( 2,  fcvt.s.w,                   2.0,  2);
+  TEST_INT_FP_OP_S( 3,  fcvt.s.w,                  -2.0, -2);
+
+  TEST_INT_FP_OP_S( 4, fcvt.s.wu,                   2.0,  2);
+  TEST_INT_FP_OP_S( 5, fcvt.s.wu,           4.2949673e9, -2);
+
+  TEST_INT_FP_OP_S( 6,  fcvt.s.l,                   2.0,  2);
+  TEST_INT_FP_OP_S( 7,  fcvt.s.l,                  -2.0, -2);
+
+  TEST_INT_FP_OP_S( 8, fcvt.s.lu,                   2.0,  2);
+  TEST_INT_FP_OP_S( 9, fcvt.s.lu,          1.8446744e19, -2);
+
+  TEST_INT_FP_OP_D(12,  fcvt.d.w,                   2.0,  2);
+  TEST_INT_FP_OP_D(13,  fcvt.d.w,                  -2.0, -2);
+
+  TEST_INT_FP_OP_D(14, fcvt.d.wu,                   2.0,  2);
+  TEST_INT_FP_OP_D(15, fcvt.d.wu,            4294967294, -2);
+
+  TEST_INT_FP_OP_D(16,  fcvt.d.l,                   2.0,  2);
+  TEST_INT_FP_OP_D(17,  fcvt.d.l,                  -2.0, -2);
+
+  TEST_INT_FP_OP_D(18, fcvt.d.lu,                   2.0,  2);
+  TEST_INT_FP_OP_D(19, fcvt.d.lu, 1.8446744073709552e19, -2);
+
+  TEST_FCVT_S_D(20, -1.5, -1.5)
+  TEST_FCVT_D_S(21, -1.5, -1.5)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S
new file mode 100644
index 0000000..e2e1686
--- /dev/null
+++ b/isa/rv64uf/fcvt_w.S
@@ -0,0 +1,83 @@
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.{s|d} instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_INT_OP_S( 2,  fcvt.w.s, -1, -1.1, rtz);
+  TEST_FP_INT_OP_S( 3,  fcvt.w.s, -1, -1.0, rtz);
+  TEST_FP_INT_OP_S( 4,  fcvt.w.s,  0, -0.9, rtz);
+  TEST_FP_INT_OP_S( 5,  fcvt.w.s,  0,  0.9, rtz);
+  TEST_FP_INT_OP_S( 6,  fcvt.w.s,  1,  1.0, rtz);
+  TEST_FP_INT_OP_S( 7,  fcvt.w.s,  1,  1.1, rtz);
+
+  TEST_FP_INT_OP_S(12, fcvt.wu.s, -1, -3.0, rtz); # invalid
+  TEST_FP_INT_OP_S(13, fcvt.wu.s, -1, -1.0, rtz); # invalid
+  TEST_FP_INT_OP_S(14, fcvt.wu.s,  0, -0.9, rtz);
+  TEST_FP_INT_OP_S(15, fcvt.wu.s,  0,  0.9, rtz);
+  TEST_FP_INT_OP_S(16, fcvt.wu.s,  1,  1.0, rtz);
+  TEST_FP_INT_OP_S(17, fcvt.wu.s,  1,  1.1, rtz);
+
+  TEST_FP_INT_OP_S(22,  fcvt.l.s, -1, -1.1, rtz);
+  TEST_FP_INT_OP_S(23,  fcvt.l.s, -1, -1.0, rtz);
+  TEST_FP_INT_OP_S(24,  fcvt.l.s,  0, -0.9, rtz);
+  TEST_FP_INT_OP_S(25,  fcvt.l.s,  0,  0.9, rtz);
+  TEST_FP_INT_OP_S(26,  fcvt.l.s,  1,  1.0, rtz);
+  TEST_FP_INT_OP_S(27,  fcvt.l.s,  1,  1.1, rtz);
+
+  TEST_FP_INT_OP_S(32, fcvt.lu.s, -1, -3.0, rtz); # invalid
+  TEST_FP_INT_OP_S(33, fcvt.lu.s, -1, -1.0, rtz); # invalid
+  TEST_FP_INT_OP_S(34, fcvt.lu.s,  0, -0.9, rtz);
+  TEST_FP_INT_OP_S(35, fcvt.lu.s,  0,  0.9, rtz);
+  TEST_FP_INT_OP_S(36, fcvt.lu.s,  1,  1.0, rtz);
+  TEST_FP_INT_OP_S(37, fcvt.lu.s,  1,  1.1, rtz);
+
+  TEST_FP_INT_OP_D(42,  fcvt.w.d, -1, -1.1, rtz);
+  TEST_FP_INT_OP_D(43,  fcvt.w.d, -1, -1.0, rtz);
+  TEST_FP_INT_OP_D(44,  fcvt.w.d,  0, -0.9, rtz);
+  TEST_FP_INT_OP_D(45,  fcvt.w.d,  0,  0.9, rtz);
+  TEST_FP_INT_OP_D(46,  fcvt.w.d,  1,  1.0, rtz);
+  TEST_FP_INT_OP_D(47,  fcvt.w.d,  1,  1.1, rtz);
+
+  TEST_FP_INT_OP_D(52, fcvt.wu.d, -1, -3.0, rtz); # invalid
+  TEST_FP_INT_OP_D(53, fcvt.wu.d, -1, -1.0, rtz); # invalid
+  TEST_FP_INT_OP_D(54, fcvt.wu.d,  0, -0.9, rtz);
+  TEST_FP_INT_OP_D(55, fcvt.wu.d,  0,  0.9, rtz);
+  TEST_FP_INT_OP_D(56, fcvt.wu.d,  1,  1.0, rtz);
+  TEST_FP_INT_OP_D(57, fcvt.wu.d,  1,  1.1, rtz);
+
+  TEST_FP_INT_OP_D(62,  fcvt.l.d, -1, -1.1, rtz);
+  TEST_FP_INT_OP_D(63,  fcvt.l.d, -1, -1.0, rtz);
+  TEST_FP_INT_OP_D(64,  fcvt.l.d,  0, -0.9, rtz);
+  TEST_FP_INT_OP_D(65,  fcvt.l.d,  0,  0.9, rtz);
+  TEST_FP_INT_OP_D(66,  fcvt.l.d,  1,  1.0, rtz);
+  TEST_FP_INT_OP_D(67,  fcvt.l.d,  1,  1.1, rtz);
+
+  TEST_FP_INT_OP_D(72, fcvt.lu.d, -1, -3.0, rtz); # invalid
+  TEST_FP_INT_OP_D(73, fcvt.lu.d, -1, -1.0, rtz); # invalid
+  TEST_FP_INT_OP_D(74, fcvt.lu.d,  0, -0.9, rtz);
+  TEST_FP_INT_OP_D(75, fcvt.lu.d,  0,  0.9, rtz);
+  TEST_FP_INT_OP_D(76, fcvt.lu.d,  1,  1.0, rtz);
+  TEST_FP_INT_OP_D(77, fcvt.lu.d,  1,  1.1, rtz);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/fmadd.S b/isa/rv64uf/fmadd.S
new file mode 100644
index 0000000..76e5e9f
--- /dev/null
+++ b/isa/rv64uf/fmadd.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP3_S( 2,  fmadd.s,                 3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S( 3,  fmadd.s,              1236.2, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S( 4,  fmadd.s,               -12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D( 5,  fmadd.d,                 3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D( 6,  fmadd.d,  1236.1999999999999, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D( 7,  fmadd.d,               -12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_S( 8, fnmadd.s,                -3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S( 9, fnmadd.s,             -1236.2, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S(10, fnmadd.s,                12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D(11, fnmadd.d,                -3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D(12, fnmadd.d, -1236.1999999999999, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D(13, fnmadd.d,                12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_S(14,  fmsub.s,                 1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S(15,  fmsub.s,                1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S(16,  fmsub.s,                -8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D(17,  fmsub.d,                 1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D(18,  fmsub.d,                1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D(19,  fmsub.d,                -8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_S(20, fnmsub.s,                -1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S(21, fnmsub.s,               -1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S(22, fnmsub.s,                 8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D(23, fnmsub.d,                -1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D(24, fnmsub.d,               -1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D(25, fnmsub.d,                 8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S
new file mode 100644
index 0000000..0041ea5
--- /dev/null
+++ b/isa/rv64uf/fmin.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.{s|d} instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_S( 2,  fmin.s,        1.0,        2.5,        1.0 );
+  TEST_FP_OP2_S( 3,  fmin.s,    -1235.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_S( 4,  fmin.s,    -1235.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_S( 5,  fmin.s,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_S( 6,  fmin.s, 0.00000001, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_S( 7,  fmin.s,       -2.0,       -1.0,       -2.0 );
+
+  TEST_FP_OP2_S(12,  fmax.s,        2.5,        2.5,        1.0 );
+  TEST_FP_OP2_S(13,  fmax.s,        1.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_S(14,  fmax.s,        1.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_S(15,  fmax.s,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_S(16,  fmax.s, 3.14159265, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_S(17,  fmax.s,       -1.0,       -1.0,       -2.0 );
+
+  TEST_FP_OP2_D(22,  fmin.d,        1.0,        2.5,        1.0 );
+  TEST_FP_OP2_D(23,  fmin.d,    -1235.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_D(24,  fmin.d,    -1235.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_D(25,  fmin.d,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_D(26,  fmin.d, 0.00000001, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_D(27,  fmin.d,       -2.0,       -1.0,       -2.0 );
+
+  TEST_FP_OP2_D(32,  fmax.d,        2.5,        2.5,        1.0 );
+  TEST_FP_OP2_D(33,  fmax.d,        1.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_D(34,  fmax.d,        1.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_D(35,  fmax.d,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_D(36,  fmax.d, 3.14159265, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_D(37,  fmax.d,       -1.0,       -1.0,       -2.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/fsgnj.S b/isa/rv64uf/fsgnj.S
new file mode 100644
index 0000000..0d2124b
--- /dev/null
+++ b/isa/rv64uf/fsgnj.S
@@ -0,0 +1,57 @@
+#*****************************************************************************
+# fsgnj.S
+#-----------------------------------------------------------------------------
+#
+# Test fsgn{j|jn|x}.{s|d} instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_S( 2,  fsgnj.s, -6.3,  6.3, -1.0 );
+  TEST_FP_OP2_S( 3,  fsgnj.s,  7.3,  7.3,  2.0 );
+  TEST_FP_OP2_S( 4,  fsgnj.s, -8.3, -8.3, -3.0 );
+  TEST_FP_OP2_S( 5,  fsgnj.s,  9.3, -9.3,  4.0 );
+
+  TEST_FP_OP2_S(12, fsgnjn.s,  6.3,  6.3, -1.0 );
+  TEST_FP_OP2_S(13, fsgnjn.s, -7.3,  7.3,  2.0 );
+  TEST_FP_OP2_S(14, fsgnjn.s,  8.3, -8.3, -3.0 );
+  TEST_FP_OP2_S(15, fsgnjn.s, -9.3, -9.3,  4.0 );
+
+  TEST_FP_OP2_S(22, fsgnjx.s, -6.3,  6.3, -1.0 );
+  TEST_FP_OP2_S(23, fsgnjx.s,  7.3,  7.3,  2.0 );
+  TEST_FP_OP2_S(24, fsgnjx.s,  8.3, -8.3, -3.0 );
+  TEST_FP_OP2_S(25, fsgnjx.s, -9.3, -9.3,  4.0 );
+
+  TEST_FP_OP2_D(32,  fsgnj.d, -6.3,  6.3, -1.0 );
+  TEST_FP_OP2_D(33,  fsgnj.d,  7.3,  7.3,  2.0 );
+  TEST_FP_OP2_D(34,  fsgnj.d, -8.3, -8.3, -3.0 );
+  TEST_FP_OP2_D(35,  fsgnj.d,  9.3, -9.3,  4.0 );
+
+  TEST_FP_OP2_D(42, fsgnjn.d,  6.3,  6.3, -1.0 );
+  TEST_FP_OP2_D(43, fsgnjn.d, -7.3,  7.3,  2.0 );
+  TEST_FP_OP2_D(44, fsgnjn.d,  8.3, -8.3, -3.0 );
+  TEST_FP_OP2_D(45, fsgnjn.d, -9.3, -9.3,  4.0 );
+
+  TEST_FP_OP2_D(52, fsgnjx.d, -6.3,  6.3, -1.0 );
+  TEST_FP_OP2_D(53, fsgnjx.d,  7.3,  7.3,  2.0 );
+  TEST_FP_OP2_D(54, fsgnjx.d,  8.3, -8.3, -3.0 );
+  TEST_FP_OP2_D(55, fsgnjx.d, -9.3, -9.3,  4.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/ldst.S b/isa/rv64uf/ldst.S
new file mode 100644
index 0000000..6e4c028
--- /dev/null
+++ b/isa/rv64uf/ldst.S
@@ -0,0 +1,30 @@
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0x4000000040400000, la a1, tdat; flw f1, 4(a1); fsw f1, 12(a1); ld a0, 8(a1))
+  TEST_CASE(3, a0, 0x400000003f800000, la a1, tdat; fld f2, 0(a1); fsd f2, 8(a1); ld a0, 8(a1))
+
+  TEST_PASSFAIL
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0x3f800000
+.word 0x40000000
+.word 0x40400000
+.word 0x40800000
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/move.S b/isa/rv64uf/move.S
new file mode 100644
index 0000000..f06e324
--- /dev/null
+++ b/isa/rv64uf/move.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that mxtf.[s,d], mftx.[s,d], mtfsr, mffsr,
+# and fsgnj[x|n].[s|d] work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+li a0, 1
+mtfsr a0
+
+  TEST_CASE(2, a1, 1, li a0, 0x1234; mtfsr a1, a0)
+  TEST_CASE(3, a0, 0x34, mffsr a0)
+  TEST_CASE(4, a0, 0x34, mffsr a0)
+
+  TEST_CASE(5, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; mxtf.s f0, a1; mftx.s a0, f0)
+  TEST_CASE(6, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; mxtf.d f1, a1; mftx.d a0, f1)
+
+  TEST_CASE(7, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; mxtf.s f0, a1; fsgnj.s f1, f0, f0; mftx.s a0, f1)
+  TEST_CASE(8, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; mxtf.s f0, a1; fsgnjx.s f1, f0, f0; mftx.s a0, f1)
+  TEST_CASE(9, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; mxtf.s f0, a1; fsgnjn.s f1, f0, f0; mftx.s a0, f1)
+  TEST_CASE(10, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; mxtf.d f1, a1; mxtf.d f2, a2; fsgnj.d f0, f1, f2; mftx.d a0, f0)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uf/structural.S b/isa/rv64uf/structural.S
new file mode 100644
index 0000000..0c74ab5
--- /dev/null
+++ b/isa/rv64uf/structural.S
@@ -0,0 +1,56 @@
+#*****************************************************************************
+# structural.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that the FPU correctly obviates structural hazards on its
+# writeback port (e.g. fadd followed by fsgnj)
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+li x25, 1
+
+li x2, 0x3FF0000000000000
+li x1, 0x3F800000
+
+#define TEST(nops, errcode)     \
+  mxtf.d  f4, x0    ;\
+  mxtf.s  f3, x0    ;\
+  mxtf.d  f2, x2    ;\
+  mxtf.s  f1, x1    ;\
+  b 1f ;\
+  .align 5        ;\
+1:fmul.d  f4, f2, f2  ;\
+  nops          ;\
+  fsgnj.s f3, f1, f1 ;\
+  mftx.d  x4, f4    ;\
+  mftx.s  x3, f3    ;\
+  beq     x1, x3, 2f  ;\
+  RVTEST_FAIL ;\
+2:beq     x2, x4, 2f  ;\
+  RVTEST_FAIL; \
+2:mxtf.d  f2, zero    ;\
+  mxtf.s  f1, zero    ;\
+
+TEST(;,2)
+TEST(nop,4)
+TEST(nop;nop,6)
+TEST(nop;nop;nop,8)
+TEST(nop;nop;nop;nop,10)
+TEST(nop;nop;nop;nop;nop,12)
+TEST(nop;nop;nop;nop;nop;nop,14)
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/Makefile b/isa/rv64ui/Makefile
new file mode 100644
index 0000000..0efb128
--- /dev/null
+++ b/isa/rv64ui/Makefile
@@ -0,0 +1,151 @@
+#=======================================================================
+# Makefile for riscv-tests
+#-----------------------------------------------------------------------
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+rv64ui_sc_tests = \
+	add addi addiw addw \
+	amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoswap_d \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
+	and andi \
+	auipc \
+	beq bge bgeu blt bltu bne \
+	div divu divuw divw \
+	example simple \
+	fence_i \
+	j jal jalr jalr_j jalr_r \
+	lb lbu lh lhu lw lwu ld \
+	lui \
+	mul mulh mulhsu mulhu mulw \
+	or ori \
+	rem remu remuw remw \
+	sb sh sw sd \
+	sll slli slliw sllw \
+	slt slti sltiu sltu \
+	sra srai sraiw sraw \
+	srl srli srliw srlw \
+	sub subw \
+	xor xori \
+
+rv64ui_mc_tests =\
+	lrsc
+
+rv64ui_sc_vec_tests = \
+	add addi addiw addw \
+	and andi \
+	lui \
+	mul mulh mulhsu mulhu mulw \
+	or ori \
+	sll slli slliw sllw \
+	slt slti sltiu sltu \
+	sra srai sraiw sraw \
+	srl srli srliw srlw \
+	sub subw \
+	xor xori \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss
+RISCV_SIM = riscv-isa-run
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.hex: %
+	elf2hex 16 16384 $< > $@
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) $< 2> $@
+
+rv64ui_p_tests_bin = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
+rv64ui_p_tests_dump = $(addsuffix .dump, $(rv64ui_p_tests_bin))
+rv64ui_p_tests_hex = $(addsuffix .hex, $(rv64ui_p_tests_bin))
+rv64ui_p_tests_out  = $(addsuffix .out,  $(rv64ui_p_tests_bin))
+
+$(rv64ui_p_tests_bin): rv64ui-p-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/scalar -T../../env/p/link.ld $< -o $@
+
+rv64ui_pm_tests_bin = $(addprefix rv64ui-pm-, $(rv64ui_mc_tests))
+rv64ui_pm_tests_dump = $(addsuffix .dump, $(rv64ui_pm_tests_bin))
+rv64ui_pm_tests_hex = $(addsuffix .hex, $(rv64ui_pm_tests_bin))
+rv64ui_pm_tests_out  = $(addsuffix .out,  $(rv64ui_pm_tests_bin))
+
+$(rv64ui_pm_tests_bin): rv64ui-pm-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pm -I../macros/scalar -T../../env/pm/link.ld $< -o $@
+
+rv64ui_v_tests_bin = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
+rv64ui_v_tests_dump = $(addsuffix .dump, $(rv64ui_v_tests_bin))
+rv64ui_v_tests_hex = $(addsuffix .hex, $(rv64ui_v_tests_bin))
+rv64ui_v_tests_out  = $(addsuffix .out,  $(rv64ui_v_tests_bin))
+
+$(rv64ui_v_tests_bin): rv64ui-v-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -std=gnu99 -O2 -I../../env/v -I../macros/scalar -T../../env/v/link.ld ../../env/v/entry.S ../../env/v/vm.c $< -lc -o $@
+
+rv64ui_p_vec_tests_bin = $(addprefix rv64ui-p-vec-, $(rv64ui_sc_vec_tests))
+rv64ui_p_vec_tests_dump = $(addsuffix .dump, $(rv64ui_p_vec_tests_bin))
+rv64ui_p_vec_tests_hex = $(addsuffix .hex, $(rv64ui_p_vec_tests_bin))
+rv64ui_p_vec_tests_out  = $(addsuffix .out,  $(rv64ui_p_vec_tests_bin))
+
+$(rv64ui_p_vec_tests_bin): rv64ui-p-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/vector -T../../env/p/link.ld $< -o $@
+
+rv64ui_pt_vec_tests_bin = $(addprefix rv64ui-pt-vec-, $(rv64ui_sc_vec_tests))
+rv64ui_pt_vec_tests_dump = $(addsuffix .dump, $(rv64ui_pt_vec_tests_bin))
+rv64ui_pt_vec_tests_hex = $(addsuffix .hex, $(rv64ui_pt_vec_tests_bin))
+rv64ui_pt_vec_tests_out  = $(addsuffix .out,  $(rv64ui_pt_vec_tests_bin))
+
+$(rv64ui_pt_vec_tests_bin): rv64ui-pt-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pt -I../macros/vector -T../../env/pt/link.ld $< -o $@
+
+rv64ui_v_vec_tests_bin = $(addprefix rv64ui-v-vec-, $(rv64ui_sc_vec_tests))
+rv64ui_v_vec_tests_dump = $(addsuffix .dump, $(rv64ui_v_vec_tests_bin))
+rv64ui_v_vec_tests_hex = $(addsuffix .hex, $(rv64ui_v_vec_tests_bin))
+rv64ui_v_vec_tests_out  = $(addsuffix .out,  $(rv64ui_v_vec_tests_bin))
+
+$(rv64ui_v_vec_tests_bin): rv64ui-v-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -std=gnu99 -O2 -I../../env/v -I../macros/vector -T../../env/v/link.ld ../../env/v/entry.S ../../env/v/vm.c $< -lc -o $@
+
+riscv-: \
+	$(rv64ui_p_tests_dump) $(rv64ui_p_tests_hex) \
+	$(rv64ui_pm_tests_dump) $(rv64ui_pm_tests_hex) \
+	$(rv64ui_v_tests_dump) $(rv64ui_v_tests_hex) \
+	$(rv64ui_p_vec_tests_dump) $(rv64ui_p_vec_tests_hex) \
+	$(rv64ui_pt_vec_tests_dump) $(rv64ui_pt_vec_tests_hex) \
+	$(rv64ui_v_vec_tests_dump) $(rv64ui_v_vec_tests_hex) \
+
+out = $(rv64ui_p_tests_out) $(rv64ui_pm_tests_out) $(rv64ui_v_tests_out) $(rv64ui_p_vec_tests_out) $(rv64ui_v_vec_tests_out)
+
+run: $(out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(out); echo;
+
+junk += \
+  $(rv64ui_p_tests_bin) $(rv64ui_p_tests_dump) $(rv64ui_p_tests_hex) $(rv64ui_p_tests_out) \
+  $(rv64ui_pm_tests_bin) $(rv64ui_pm_tests_dump) $(rv64ui_pm_tests_hex) $(rv64ui_pm_tests_out) \
+  $(rv64ui_v_tests_bin) $(rv64ui_v_tests_dump) $(rv64ui_v_tests_hex) $(rv64ui_v_tests_out) \
+  $(rv64ui_p_vec_tests_bin) $(rv64ui_p_vec_tests_dump) $(rv64ui_p_vec_tests_hex) $(rv64ui_p_vec_tests_out) \
+  $(rv64ui_pt_vec_tests_bin) $(rv64ui_pt_vec_tests_dump) $(rv64ui_pt_vec_tests_hex) $(rv64ui_pt_vec_tests_out) \
+  $(rv64ui_v_vec_tests_bin) $(rv64ui_v_vec_tests_dump) $(rv64ui_v_vec_tests_hex) $(rv64ui_v_vec_tests_out) \
+
+#------------------------------------------------------------
+# Default
+
+all: riscv-
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/isa/rv64ui/add.S b/isa/rv64ui/add.S
new file mode 100644
index 0000000..2b45eda
--- /dev/null
+++ b/isa/rv64ui/add.S
@@ -0,0 +1,83 @@
+#*****************************************************************************
+# add.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  add, 0x00000002, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  add, 0x0000000a, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, add, 32, 32 );
+  TEST_RR_ZEROSRC12( 37, add, 0 );
+  TEST_RR_ZERODEST( 38, add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/addi.S b/isa/rv64ui/addi.S
new file mode 100644
index 0000000..c32d729
--- /dev/null
+++ b/isa/rv64ui/addi.S
@@ -0,0 +1,69 @@
+#*****************************************************************************
+# addi.S
+#-----------------------------------------------------------------------------
+#
+# Test addi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  addi, 0x00000000, 0x00000000, 0x000 );
+  TEST_IMM_OP( 3,  addi, 0x00000002, 0x00000001, 0x001 );
+  TEST_IMM_OP( 4,  addi, 0x0000000a, 0x00000003, 0x007 );
+
+  TEST_IMM_OP( 5,  addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 6,  addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 7,  addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 8,  addi, 0x00000000000007ff, 0x00000000, 0x7ff );
+  TEST_IMM_OP( 9,  addi, 0x000000007fffffff, 0x7fffffff, 0x000 );
+  TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff );
+
+  TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
+
+  TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
+  TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
+  TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13,  9 );
+
+  TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
+  TEST_IMM_ZERODEST( 25, addi, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/addiw.S b/isa/rv64ui/addiw.S
new file mode 100644
index 0000000..db9220a
--- /dev/null
+++ b/isa/rv64ui/addiw.S
@@ -0,0 +1,69 @@
+#*****************************************************************************
+# addiw.S
+#-----------------------------------------------------------------------------
+#
+# Test addiw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  addiw, 0x00000000, 0x00000000, 0x000 );
+  TEST_IMM_OP( 3,  addiw, 0x00000002, 0x00000001, 0x001 );
+  TEST_IMM_OP( 4,  addiw, 0x0000000a, 0x00000003, 0x007 );
+
+  TEST_IMM_OP( 5,  addiw, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 6,  addiw, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 7,  addiw, 0x000000007ffff800, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 8,  addiw, 0x00000000000007ff, 0x00000000, 0x7ff );
+  TEST_IMM_OP( 9,  addiw, 0x000000007fffffff, 0x7fffffff, 0x000 );
+  TEST_IMM_OP( 10, addiw, 0xffffffff800007fe, 0x7fffffff, 0x7ff );
+
+  TEST_IMM_OP( 11, addiw, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 12, addiw, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 13, addiw, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 14, addiw, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 15, addiw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
+
+  TEST_IMM_OP( 16, addiw, 0xffffffff80000000, 0x7fffffff, 0x001 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, addiw, 24, 13, 11 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, addiw, 24, 13, 11 );
+  TEST_IMM_DEST_BYPASS( 19, 1, addiw, 23, 13, 10 );
+  TEST_IMM_DEST_BYPASS( 20, 2, addiw, 22, 13,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, addiw, 24, 13, 11 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, addiw, 23, 13, 10 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, addiw, 22, 13,  9 );
+
+  TEST_IMM_ZEROSRC1( 24, addiw, 32, 32 );
+  TEST_IMM_ZERODEST( 25, addiw, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/addw.S b/isa/rv64ui/addw.S
new file mode 100644
index 0000000..069ea46
--- /dev/null
+++ b/isa/rv64ui/addw.S
@@ -0,0 +1,83 @@
+#*****************************************************************************
+# addw.S
+#-----------------------------------------------------------------------------
+#
+# Test addw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  addw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  addw, 0x00000002, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  addw, 0x0000000a, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  addw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  addw, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  addw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  addw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  addw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, addw, 0xffffffff80007ffe, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, addw, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, addw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, addw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, addw, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, addw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, addw, 0xffffffff80000000, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, addw, 24, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, addw, 25, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, addw, 26, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, addw, 24, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, addw, 25, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, addw, 26, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, addw, 26, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, addw, 26, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, addw, 26, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, addw, 26, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, addw, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, addw, 32, 32 );
+  TEST_RR_ZEROSRC12( 37, addw, 0 );
+  TEST_RR_ZERODEST( 38, addw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/amoadd_d.S b/isa/rv64ui/amoadd_d.S
new file mode 100644
index 0000000..21d534c
--- /dev/null
+++ b/isa/rv64ui/amoadd_d.S
@@ -0,0 +1,62 @@
+#*****************************************************************************
+# amoadd_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoadd.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff7ffff800, \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    amoadd.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amoadd_w.S b/isa/rv64ui/amoadd_w.S
new file mode 100644
index 0000000..4c71ac8
--- /dev/null
+++ b/isa/rv64ui/amoadd_w.S
@@ -0,0 +1,63 @@
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoadd.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x000000007ffff800, \
+    li  a1, 0xffffffff80000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoadd.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+    .bss
+    .align 3
+amo_operand:
+    .dword 0
+    .skip 65536
diff --git a/isa/rv64ui/amoand_d.S b/isa/rv64ui/amoand_d.S
new file mode 100644
index 0000000..0c4985c
--- /dev/null
+++ b/isa/rv64ui/amoand_d.S
@@ -0,0 +1,63 @@
+#*****************************************************************************
+# amoand_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoand.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff80000000, \
+    li  a1, 0x0000000080000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    amoand.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amoand_w.S b/isa/rv64ui/amoand_w.S
new file mode 100644
index 0000000..0433860
--- /dev/null
+++ b/isa/rv64ui/amoand_w.S
@@ -0,0 +1,63 @@
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoand.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff80000000, \
+    li  a1, 0x0000000080000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoand.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amomax_d.S b/isa/rv64ui/amomax_d.S
new file mode 100644
index 0000000..a0dc2aa
--- /dev/null
+++ b/isa/rv64ui/amomax_d.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amomax.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 1; \
+    sd x0, 0(a3); \
+    amomax.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 1, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amomax_w.S b/isa/rv64ui/amomax_w.S
new file mode 100644
index 0000000..0fe3352
--- /dev/null
+++ b/isa/rv64ui/amomax_w.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 1; \
+    sw x0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 1, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amomaxu_d.S b/isa/rv64ui/amomaxu_d.S
new file mode 100644
index 0000000..9dc13e4
--- /dev/null
+++ b/isa/rv64ui/amomaxu_d.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amomaxu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sd x0, 0(a3); \
+    amomaxu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amomaxu_w.S b/isa/rv64ui/amomaxu_w.S
new file mode 100644
index 0000000..8e774b6
--- /dev/null
+++ b/isa/rv64ui/amomaxu_w.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomaxu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sw x0, 0(a3); \
+    amomaxu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amomin_d.S b/isa/rv64ui/amomin_d.S
new file mode 100644
index 0000000..168ae3c
--- /dev/null
+++ b/isa/rv64ui/amomin_d.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amomin.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sd x0, 0(a3); \
+    amomin.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amomin_w.S b/isa/rv64ui/amomin_w.S
new file mode 100644
index 0000000..e6822d8
--- /dev/null
+++ b/isa/rv64ui/amomin_w.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomin.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sw x0, 0(a3); \
+    amomin.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amominu_d.S b/isa/rv64ui/amominu_d.S
new file mode 100644
index 0000000..9572d95
--- /dev/null
+++ b/isa/rv64ui/amominu_d.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amominu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sd x0, 0(a3); \
+    amominu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amominu_w.S b/isa/rv64ui/amominu_w.S
new file mode 100644
index 0000000..cf2f516
--- /dev/null
+++ b/isa/rv64ui/amominu_w.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amominu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sw x0, 0(a3); \
+    amominu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amoor_d.S b/isa/rv64ui/amoor_d.S
new file mode 100644
index 0000000..ce1a843
--- /dev/null
+++ b/isa/rv64ui/amoor_d.S
@@ -0,0 +1,63 @@
+#*****************************************************************************
+# amoor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoor.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 1; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    amoor.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amoor_w.S b/isa/rv64ui/amoor_w.S
new file mode 100644
index 0000000..784aee7
--- /dev/null
+++ b/isa/rv64ui/amoor_w.S
@@ -0,0 +1,63 @@
+#*****************************************************************************
+# amoor.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoor.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 1; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoor.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amoswap_d.S b/isa/rv64ui/amoswap_d.S
new file mode 100644
index 0000000..b78e653
--- /dev/null
+++ b/isa/rv64ui/amoswap_d.S
@@ -0,0 +1,63 @@
+#*****************************************************************************
+# amoswap.d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoswap.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 0x0000000080000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    add a5, a5, a4; \
+    ld  x0, 0(a5); \
+    amoswap.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/amoswap_w.S b/isa/rv64ui/amoswap_w.S
new file mode 100644
index 0000000..174676b
--- /dev/null
+++ b/isa/rv64ui/amoswap_w.S
@@ -0,0 +1,63 @@
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoswap.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 0x0000000080000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoswap.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv64ui/and.S b/isa/rv64ui/and.S
new file mode 100644
index 0000000..75ca9a6
--- /dev/null
+++ b/isa/rv64ui/and.S
@@ -0,0 +1,67 @@
+#*****************************************************************************
+# and.S
+#-----------------------------------------------------------------------------
+#
+# Test and instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, and, 0 );
+  TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/andi.S b/isa/rv64ui/andi.S
new file mode 100644
index 0000000..b7a2d81
--- /dev/null
+++ b/isa/rv64ui/andi.S
@@ -0,0 +1,53 @@
+#*****************************************************************************
+# andi.S
+#-----------------------------------------------------------------------------
+#
+# Test andi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
+  TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
+  TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+  TEST_IMM_DEST_BYPASS( 8,  1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 9,  2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+  TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
+
+  TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/auipc.S b/isa/rv64ui/auipc.S
new file mode 100644
index 0000000..9b291b5
--- /dev/null
+++ b/isa/rv64ui/auipc.S
@@ -0,0 +1,35 @@
+#*****************************************************************************
+# auipc.S
+#-----------------------------------------------------------------------------
+#
+# Test auipc instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, -4096+8, \
+    auipc a0, 0x00001; \
+    jal 1f; \
+    1: sub a0, ra, a0; \
+  )
+
+  TEST_CASE(3, a0, 4096+8, \
+    auipc a0, 0xfffff; \
+    jal 1f; \
+    1: sub a0, ra, a0; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/beq.S b/isa/rv64ui/beq.S
new file mode 100644
index 0000000..32d6275
--- /dev/null
+++ b/isa/rv64ui/beq.S
@@ -0,0 +1,71 @@
+#*****************************************************************************
+# beq.S
+#-----------------------------------------------------------------------------
+#
+# Test beq instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, beq,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, beq,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, beq,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN( 6, beq,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, beq, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, beq,  1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    beq x0, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/bge.S b/isa/rv64ui/bge.S
new file mode 100644
index 0000000..908b5d1
--- /dev/null
+++ b/isa/rv64ui/bge.S
@@ -0,0 +1,74 @@
+#*****************************************************************************
+# bge.S
+#-----------------------------------------------------------------------------
+#
+# Test bge instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bge,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, bge,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
+  TEST_BR2_OP_TAKEN( 5, bge,  1,  0 );
+  TEST_BR2_OP_TAKEN( 6, bge,  1, -1 );
+  TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bge,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN(  9, bge, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
+  TEST_BR2_OP_NOTTAKEN( 11, bge, -2,  1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 24, x1, 3, \
+    li  x1, 1; \
+    bge x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/bgeu.S b/isa/rv64ui/bgeu.S
new file mode 100644
index 0000000..100e247
--- /dev/null
+++ b/isa/rv64ui/bgeu.S
@@ -0,0 +1,74 @@
+#*****************************************************************************
+# bgeu.S
+#-----------------------------------------------------------------------------
+#
+# Test bgeu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bgeu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_NOTTAKEN(  9, bgeu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 24, x1, 3, \
+    li  x1, 1; \
+    bgeu x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/blt.S b/isa/rv64ui/blt.S
new file mode 100644
index 0000000..aa995d7
--- /dev/null
+++ b/isa/rv64ui/blt.S
@@ -0,0 +1,71 @@
+#*****************************************************************************
+# blt.S
+#-----------------------------------------------------------------------------
+#
+# Test blt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, blt,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, blt, -1,  1 );
+  TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, blt,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 6, blt,  1, -1 );
+  TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
+  TEST_BR2_OP_NOTTAKEN( 8, blt,  1, -2 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    blt x0, x1, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/bltu.S b/isa/rv64ui/bltu.S
new file mode 100644
index 0000000..73ad3ab
--- /dev/null
+++ b/isa/rv64ui/bltu.S
@@ -0,0 +1,71 @@
+#*****************************************************************************
+# bltu.S
+#-----------------------------------------------------------------------------
+#
+# Test bltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
+
+  TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    bltu x0, x1, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/bne.S b/isa/rv64ui/bne.S
new file mode 100644
index 0000000..5ab2dee
--- /dev/null
+++ b/isa/rv64ui/bne.S
@@ -0,0 +1,71 @@
+#*****************************************************************************
+# bne.S
+#-----------------------------------------------------------------------------
+#
+# Test bne instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bne,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, bne,  1,  0 );
+  TEST_BR2_OP_TAKEN( 4, bne, -1,  1 );
+  TEST_BR2_OP_TAKEN( 5, bne,  1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 6, bne,  0,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, bne,  1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    bne x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/div.S b/isa/rv64ui/div.S
new file mode 100644
index 0000000..13b118b
--- /dev/null
+++ b/isa/rv64ui/div.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, div,  3,  20,   6 );
+  TEST_RR_OP( 3, div, -3, -20,   6 );
+  TEST_RR_OP( 4, div, -3,  20,  -6 );
+  TEST_RR_OP( 5, div,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, div, -1<<63, -1<<63,  1 );
+  TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
+
+  TEST_RR_OP( 8, div, -1, -1<<63, 0 );
+  TEST_RR_OP( 9, div, -1,      1, 0 );
+  TEST_RR_OP(10, div, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/divu.S b/isa/rv64ui/divu.S
new file mode 100644
index 0000000..3fa4bdb
--- /dev/null
+++ b/isa/rv64ui/divu.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divu,                   3,  20,   6 );
+  TEST_RR_OP( 3, divu, 3074457345618258599, -20,   6 );
+  TEST_RR_OP( 4, divu,                   0,  20,  -6 );
+  TEST_RR_OP( 5, divu,                   0, -20,  -6 );
+
+  TEST_RR_OP( 6, divu, -1<<63, -1<<63,  1 );
+  TEST_RR_OP( 7, divu,     0,  -1<<63, -1 );
+
+  TEST_RR_OP( 8, divu, -1, -1<<63, 0 );
+  TEST_RR_OP( 9, divu, -1,      1, 0 );
+  TEST_RR_OP(10, divu, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/divuw.S b/isa/rv64ui/divuw.S
new file mode 100644
index 0000000..21fd092
--- /dev/null
+++ b/isa/rv64ui/divuw.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# divuw.S
+#-----------------------------------------------------------------------------
+#
+# Test divuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divuw,         3,  20,   6 );
+  TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32,   6 );
+  TEST_RR_OP( 4, divuw,         0,  20,  -6 );
+  TEST_RR_OP( 5, divuw,         0, -20,  -6 );
+
+  TEST_RR_OP( 6, divuw, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divuw, 0,      -1<<31, -1 );
+
+  TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divuw, -1,      1, 0 );
+  TEST_RR_OP(10, divuw, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/divw.S b/isa/rv64ui/divw.S
new file mode 100644
index 0000000..847fdb0
--- /dev/null
+++ b/isa/rv64ui/divw.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# divw.S
+#-----------------------------------------------------------------------------
+#
+# Test divw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divw,  3,  20,   6 );
+  TEST_RR_OP( 3, divw, -3, -20,   6 );
+  TEST_RR_OP( 4, divw, -3,  20,  -6 );
+  TEST_RR_OP( 5, divw,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, divw, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divw, -1,      1, 0 );
+  TEST_RR_OP(10, divw, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/example.S b/isa/rv64ui/example.S
new file mode 100644
index 0000000..a667035
--- /dev/null
+++ b/isa/rv64ui/example.S
@@ -0,0 +1,25 @@
+#*****************************************************************************
+# simple.S
+#-----------------------------------------------------------------------------
+#
+# This is the most basic self checking test. If your simulator does not
+# pass thiss then there is little chance that it will pass any of the
+# more complicated self checking tests.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/fence_i.S b/isa/rv64ui/fence_i.S
new file mode 100644
index 0000000..4e79b41
--- /dev/null
+++ b/isa/rv64ui/fence_i.S
@@ -0,0 +1,51 @@
+#*****************************************************************************
+# fence_i.S
+#-----------------------------------------------------------------------------
+#
+# Test self-modifying code and the fence.i instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+li a3, 111
+la a0, 3f
+la a1, 1f
+la a2, 2f
+lw a0, 0(a0)
+
+# test I$ hit
+.align 6
+sw a0, 0(a1)
+fence.i
+
+1: addi a3, a3, 222
+TEST_CASE( 2, a3, 444, nop )
+
+# test prefetcher hit
+li a4, 100
+1: addi a4, a4, -1
+bnez a4, 1b
+
+sw a0, 0(a2)
+fence.i
+
+.align 6
+2: addi a3, a3, 555
+TEST_CASE( 3, a3, 777, nop )
+
+3: addi a3, a3, 333
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/j.S b/isa/rv64ui/j.S
new file mode 100644
index 0000000..5b0ea3d
--- /dev/null
+++ b/isa/rv64ui/j.S
@@ -0,0 +1,47 @@
+#*****************************************************************************
+# j.S
+#-----------------------------------------------------------------------------
+#
+# Test j instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test basic
+  #-------------------------------------------------------------
+
+  li  x28, 2;
+  j test_2;
+  j fail;
+test_2:
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 3, x1, 3, \
+    li  x1, 1; \
+    j 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/jal.S b/isa/rv64ui/jal.S
new file mode 100644
index 0000000..f51ce1b
--- /dev/null
+++ b/isa/rv64ui/jal.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# jal.S
+#-----------------------------------------------------------------------------
+#
+# Test jal instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  x28, 2
+  li  ra, 0
+
+linkaddr_2:
+  jal target_2
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la  x2, linkaddr_2
+  addi x2, x2, 4
+  bne x2, ra, fail
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 3, x2, 3, \
+    li  x2, 1; \
+    jal 1f; \
+    addi x2, x2, 1; \
+    addi x2, x2, 1; \
+    addi x2, x2, 1; \
+    addi x2, x2, 1; \
+1:  addi x2, x2, 1; \
+    addi x2, x2, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S
new file mode 100644
index 0000000..9eef93b
--- /dev/null
+++ b/isa/rv64ui/jalr.S
@@ -0,0 +1,86 @@
+#*****************************************************************************
+# jalr.S
+#-----------------------------------------------------------------------------
+#
+# Test jalr instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  x28, 2
+  li  x31, 0
+  la  x2, target_2
+
+linkaddr_2:
+  jalr x19, x2, 0
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la  x1, linkaddr_2
+  addi x1, x1, 4
+  bne x1, x19, fail
+
+  #-------------------------------------------------------------
+  # Test 3: Check r0 target and that r31 is not modified
+  #-------------------------------------------------------------
+
+test_3:
+  li  x28, 3
+  li  x31, 0
+  la  x3, target_3
+
+linkaddr_3:
+  jalr x0, x3, 0
+  nop
+
+  j fail
+
+target_3:
+  bne x31, x0, fail
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
+  TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
+  TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 7, x1, 4, \
+    li  x1, 1; \
+    la  x2, 1f;
+    jalr x19, x2, -4; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/jalr_j.S b/isa/rv64ui/jalr_j.S
new file mode 100644
index 0000000..5a7b069
--- /dev/null
+++ b/isa/rv64ui/jalr_j.S
@@ -0,0 +1,86 @@
+#*****************************************************************************
+# jalr_j.S
+#-----------------------------------------------------------------------------
+#
+# Test jalr.j instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  x28, 2
+  li  x31, 0
+  la  x2, target_2
+
+linkaddr_2:
+  jalr.j x19, x2, 0
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la  x1, linkaddr_2
+  addi x1, x1, 4
+  bne x1, x19, fail
+
+  #-------------------------------------------------------------
+  # Test 3: Check r0 target and that r31 is not modified
+  #-------------------------------------------------------------
+
+test_3:
+  li  x28, 3
+  li  x31, 0
+  la  x3, target_3
+
+linkaddr_3:
+  jalr.j x0, x3, 0
+  nop
+
+  j fail
+
+target_3:
+  bne x31, x0, fail
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_JALR_SRC1_BYPASS( 4, 0, jalr.j );
+  TEST_JALR_SRC1_BYPASS( 5, 1, jalr.j );
+  TEST_JALR_SRC1_BYPASS( 6, 2, jalr.j );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 7, x1, 3, \
+    li  x1, 1; \
+    la  x2, 1f;
+    jalr.j x19, x2, 0; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/jalr_r.S b/isa/rv64ui/jalr_r.S
new file mode 100644
index 0000000..67a3a9e
--- /dev/null
+++ b/isa/rv64ui/jalr_r.S
@@ -0,0 +1,86 @@
+#*****************************************************************************
+# jalr_r.S
+#-----------------------------------------------------------------------------
+#
+# Test jalr.r instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  x28, 2
+  li  x31, 0
+  la  x2, target_2
+
+linkaddr_2:
+  jalr.r x19, x2, 0
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la  x1, linkaddr_2
+  addi x1, x1, 4
+  bne x1, x19, fail
+
+  #-------------------------------------------------------------
+  # Test 3: Check r0 target and that r31 is not modified
+  #-------------------------------------------------------------
+
+test_3:
+  li  x28, 3
+  li  x31, 0
+  la  x3, target_3
+
+linkaddr_3:
+  jalr.r x0, x3, 0
+  nop
+
+  j fail
+
+target_3:
+  bne x31, x0, fail
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_JALR_SRC1_BYPASS( 4, 0, jalr.r );
+  TEST_JALR_SRC1_BYPASS( 5, 1, jalr.r );
+  TEST_JALR_SRC1_BYPASS( 6, 2, jalr.r );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 7, x1, 3, \
+    li  x1, 1; \
+    la  x2, 1f;
+    jalr.r x19, x2, 0; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lb.S b/isa/rv64ui/lb.S
new file mode 100644
index 0000000..bbb4879
--- /dev/null
+++ b/isa/rv64ui/lb.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# lb.S
+#-----------------------------------------------------------------------------
+#
+# Test lb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0,  tdat );
+  TEST_LD_OP( 3, lb, 0x0000000000000000, 1,  tdat );
+  TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2,  tdat );
+  TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 );
+  TEST_LD_OP( 7, lb, 0x0000000000000000, -2,  tdat4 );
+  TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1,  tdat4 );
+  TEST_LD_OP( 9, lb, 0x000000000000000f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0xffffffffffffffff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lb x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x0000000000000000, \
+    la  x1, tdat; \
+    addi x1, x1, -6; \
+    lb x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lb  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lb  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xff
+tdat2:  .byte 0x00
+tdat3:  .byte 0xf0
+tdat4:  .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lbu.S b/isa/rv64ui/lbu.S
new file mode 100644
index 0000000..03f1585
--- /dev/null
+++ b/isa/rv64ui/lbu.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# lbu.S
+#-----------------------------------------------------------------------------
+#
+# Test lbu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lbu, 0x0000000000000000, 1,  tdat );
+  TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2,  tdat );
+  TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 );
+  TEST_LD_OP( 7, lbu, 0x0000000000000000, -2,  tdat4 );
+  TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1,  tdat4 );
+  TEST_LD_OP( 9, lbu, 0x000000000000000f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x00000000000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lbu x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x0000000000000000, \
+    la  x1, tdat; \
+    addi x1, x1, -6; \
+    lbu x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lbu  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lbu  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xff
+tdat2:  .byte 0x00
+tdat3:  .byte 0xf0
+tdat4:  .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/ld.S b/isa/rv64ui/ld.S
new file mode 100644
index 0000000..d59fe2e
--- /dev/null
+++ b/isa/rv64ui/ld.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# ld.S
+#-----------------------------------------------------------------------------
+#
+# Test ld instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0,  tdat );
+  TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8,  tdat );
+  TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat );
+  TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 );
+  TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 );
+  TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8,  tdat4 );
+  TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x00ff00ff00ff00ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    ld x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0xff00ff00ff00ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -3; \
+    ld x3, 11(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    ld  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    ld  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .dword 0x00ff00ff00ff00ff
+tdat2:  .dword 0xff00ff00ff00ff00
+tdat3:  .dword 0x0ff00ff00ff00ff0
+tdat4:  .dword 0xf00ff00ff00ff00f
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lh.S b/isa/rv64ui/lh.S
new file mode 100644
index 0000000..f04665a
--- /dev/null
+++ b/isa/rv64ui/lh.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# lh.S
+#-----------------------------------------------------------------------------
+#
+# Test lh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lh, 0x00000000000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2,  tdat );
+  TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4,  tdat );
+  TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lh, 0x00000000000000ff, -6,  tdat4 );
+  TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4,  tdat4 );
+  TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2,  tdat4 );
+  TEST_LD_OP( 9, lh, 0xfffffffffffff00f,  0, tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x00000000000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lh x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0xffffffffffffff00, \
+    la  x1, tdat; \
+    addi x1, x1, -5; \
+    lh x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lh  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lh  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0x00ff
+tdat2:  .half 0xff00
+tdat3:  .half 0x0ff0
+tdat4:  .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lhu.S b/isa/rv64ui/lhu.S
new file mode 100644
index 0000000..57661fa
--- /dev/null
+++ b/isa/rv64ui/lhu.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# lhu.S
+#-----------------------------------------------------------------------------
+#
+# Test lhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2,  tdat );
+  TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4,  tdat );
+  TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6,  tdat4 );
+  TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4,  tdat4 );
+  TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2,  tdat4 );
+  TEST_LD_OP( 9, lhu, 0x000000000000f00f,  0, tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x00000000000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lhu x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x000000000000ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -5; \
+    lhu x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lhu  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lhu  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0x00ff
+tdat2:  .half 0xff00
+tdat3:  .half 0x0ff0
+tdat4:  .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lrsc.S b/isa/rv64ui/lrsc.S
new file mode 100644
index 0000000..ec6748c
--- /dev/null
+++ b/isa/rv64ui/lrsc.S
@@ -0,0 +1,64 @@
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+#
+# Test LR/SC instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+# wait for all cores ao boot
+la a0, coreid
+li a1, 1
+amoadd.w a2, a1, 0(a0)
+lw a3, 4(x0)
+1: lw a1, 0(a0)
+blt a1, a3, 1b
+
+# have each core add its coreid ao foo 1000 aimes
+la a0, foo
+li a1, 1000
+1: lr.w a4, 0(a0)
+#amoadd.w x0, a2, 0(a0)
+add a4, a4, a2
+sc.w a4, a4, 0(a0)
+bnez a4, 1b
+add a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores ao finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, 0(a0)
+1: lw a1, 0(a0)
+blt a1, a3, 1b
+fence
+
+# expected result is 1000*ncores*(ncores-1)/2
+la a0, foo
+li a1, 500
+mul a1, a1, a3
+add a2, a3, -1
+mul a1, a1, a2
+lw a2, 0(a0)
+bne a2, a1, 1f
+RVTEST_PASS
+1: RVTEST_FAIL
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lui.S b/isa/rv64ui/lui.S
new file mode 100644
index 0000000..435fc4f
--- /dev/null
+++ b/isa/rv64ui/lui.S
@@ -0,0 +1,34 @@
+#*****************************************************************************
+# lui.S
+#-----------------------------------------------------------------------------
+#
+# Test lui instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 );
+  TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1);
+  TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20);
+  TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20);
+
+  TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lw.S b/isa/rv64ui/lw.S
new file mode 100644
index 0000000..ac4c91f
--- /dev/null
+++ b/isa/rv64ui/lw.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# lw.S
+#-----------------------------------------------------------------------------
+#
+# Test lw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0,  tdat );
+  TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4,  tdat );
+  TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8,  tdat );
+  TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 );
+  TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8,  tdat4 );
+  TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4,  tdat4 );
+  TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x0000000000ff00ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lw x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0xffffffffff00ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -3; \
+    lw x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lw  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lw  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0x00ff00ff
+tdat2:  .word 0xff00ff00
+tdat3:  .word 0x0ff00ff0
+tdat4:  .word 0xf00ff00f
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/lwu.S b/isa/rv64ui/lwu.S
new file mode 100644
index 0000000..33d5601
--- /dev/null
+++ b/isa/rv64ui/lwu.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# lwu.S
+#-----------------------------------------------------------------------------
+#
+# Test lwu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0,  tdat );
+  TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4,  tdat );
+  TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8,  tdat );
+  TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 );
+  TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8,  tdat4 );
+  TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4,  tdat4 );
+  TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x0000000000ff00ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lwu x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x00000000ff00ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -3; \
+    lwu x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lwu x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lwu x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0x00ff00ff
+tdat2:  .word 0xff00ff00
+tdat3:  .word 0x0ff00ff0
+tdat4:  .word 0xf00ff00f
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/mul.S b/isa/rv64ui/mul.S
new file mode 100644
index 0000000..79fd332
--- /dev/null
+++ b/isa/rv64ui/mul.S
@@ -0,0 +1,73 @@
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mul, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mul, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mul, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP(30,  mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
+  TEST_RR_OP(31,  mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mul, 0 );
+  TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/mulh.S b/isa/rv64ui/mulh.S
new file mode 100644
index 0000000..0473d22
--- /dev/null
+++ b/isa/rv64ui/mulh.S
@@ -0,0 +1,70 @@
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulh, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulh, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 );
+
+  TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 );
+  TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 );
+  TEST_RR_ZEROSRC12( 28, mulh, 0 );
+  TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/mulhsu.S b/isa/rv64ui/mulhsu.S
new file mode 100644
index 0000000..b78e1c5
--- /dev/null
+++ b/isa/rv64ui/mulhsu.S
@@ -0,0 +1,70 @@
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 );
+  TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 );
+  TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+  TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/mulhu.S b/isa/rv64ui/mulhu.S
new file mode 100644
index 0000000..b49c88e
--- /dev/null
+++ b/isa/rv64ui/mulhu.S
@@ -0,0 +1,73 @@
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP(30,  mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
+  TEST_RR_OP(31,  mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 );
+  TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 );
+  TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+  TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/mulw.S b/isa/rv64ui/mulw.S
new file mode 100644
index 0000000..49ff073
--- /dev/null
+++ b/isa/rv64ui/mulw.S
@@ -0,0 +1,70 @@
+#*****************************************************************************
+# mulw.S
+#-----------------------------------------------------------------------------
+#
+# Test mulw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulw, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulw, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mulw, 0 );
+  TEST_RR_ZERODEST( 29, mulw, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/or.S b/isa/rv64ui/or.S
new file mode 100644
index 0000000..81daae1
--- /dev/null
+++ b/isa/rv64ui/or.S
@@ -0,0 +1,67 @@
+#*****************************************************************************
+# or.S
+#-----------------------------------------------------------------------------
+#
+# Test or instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, or, 0 );
+  TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/ori.S b/isa/rv64ui/ori.S
new file mode 100644
index 0000000..5f6c018
--- /dev/null
+++ b/isa/rv64ui/ori.S
@@ -0,0 +1,53 @@
+#*****************************************************************************
+# ori.S
+#-----------------------------------------------------------------------------
+#
+# Test ori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f );
+  TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
+  TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 8,  1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
+  TEST_IMM_DEST_BYPASS( 9,  2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f );
+  TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/rdnpc.S b/isa/rv64ui/rdnpc.S
new file mode 100644
index 0000000..09253b3
--- /dev/null
+++ b/isa/rv64ui/rdnpc.S
@@ -0,0 +1,29 @@
+#*****************************************************************************
+# rdnpc_w.S
+#-----------------------------------------------------------------------------
+#
+# Test rdnpc instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 4, \
+    rdnpc a0; \
+    jal 1f; \
+    1: sub a0, ra, a0; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/rem.S b/isa/rv64ui/rem.S
new file mode 100644
index 0000000..40dd68c
--- /dev/null
+++ b/isa/rv64ui/rem.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, rem,  2,  20,   6 );
+  TEST_RR_OP( 3, rem, -2, -20,   6 );
+  TEST_RR_OP( 4, rem,  2,  20,  -6 );
+  TEST_RR_OP( 5, rem, -2, -20,  -6 );
+
+  TEST_RR_OP( 6, rem,  0, -1<<63,  1 );
+  TEST_RR_OP( 7, rem,  0, -1<<63, -1 );
+
+  TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
+  TEST_RR_OP( 9, rem,      1,      1, 0 );
+  TEST_RR_OP(10, rem,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/remu.S b/isa/rv64ui/remu.S
new file mode 100644
index 0000000..9089a3d
--- /dev/null
+++ b/isa/rv64ui/remu.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remu,   2,  20,   6 );
+  TEST_RR_OP( 3, remu,   2, -20,   6 );
+  TEST_RR_OP( 4, remu,  20,  20,  -6 );
+  TEST_RR_OP( 5, remu, -20, -20,  -6 );
+
+  TEST_RR_OP( 6, remu,      0, -1<<63,  1 );
+  TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
+
+  TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
+  TEST_RR_OP( 9, remu,      1,      1, 0 );
+  TEST_RR_OP(10, remu,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/remuw.S b/isa/rv64ui/remuw.S
new file mode 100644
index 0000000..8b978b5
--- /dev/null
+++ b/isa/rv64ui/remuw.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# remuw.S
+#-----------------------------------------------------------------------------
+#
+# Test remuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remuw,   2,  20,   6 );
+  TEST_RR_OP( 3, remuw,   2, -20,   6 );
+  TEST_RR_OP( 4, remuw,  20,  20,  -6 );
+  TEST_RR_OP( 5, remuw, -20, -20,  -6 );
+
+  TEST_RR_OP( 6, remuw,      0, -1<<31,  1 );
+  TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, remuw,      1,      1, 0 );
+  TEST_RR_OP(10, remuw,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/remw.S b/isa/rv64ui/remw.S
new file mode 100644
index 0000000..26820e3
--- /dev/null
+++ b/isa/rv64ui/remw.S
@@ -0,0 +1,39 @@
+#*****************************************************************************
+# remw.S
+#-----------------------------------------------------------------------------
+#
+# Test remw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remw,  2,  20,   6 );
+  TEST_RR_OP( 3, remw, -2, -20,   6 );
+  TEST_RR_OP( 4, remw,  2,  20,  -6 );
+  TEST_RR_OP( 5, remw, -2, -20,  -6 );
+
+  TEST_RR_OP( 6, remw,  0, -1<<31,  1 );
+  TEST_RR_OP( 7, remw,  0, -1<<31, -1 );
+
+  TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, remw,      1,      1, 0 );
+  TEST_RR_OP(10, remw,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sb.S b/isa/rv64ui/sb.S
new file mode 100644
index 0000000..e072cd5
--- /dev/null
+++ b/isa/rv64ui/sb.S
@@ -0,0 +1,100 @@
+#*****************************************************************************
+# sb.S
+#-----------------------------------------------------------------------------
+#
+# Test sb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat );
+  TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat );
+#ifdef __RISCVEL
+  TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat );
+#elif defined(__RISCVEB)
+#else
+  TEST_ST_OP( 4, lh, sb, 0xffffffffffffa0ef, 2, tdat );
+#error unknown endianness!
+#endif
+  TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 );
+  TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 );
+  TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 );
+  TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0,  tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x78, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sb x2, 32(x4); \
+    lb x3, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0xffffffffffffff98, \
+    la  x1, tdat9; \
+    li  x2, 0x00003098; \
+    addi x1, x1, -6; \
+    sb x2, 7(x1); \
+    la  x4, tdat10; \
+    lb x3, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
+
+  li a0, 0xef
+  la a1, tdat
+  sb a0, 3(a1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xef
+tdat2:  .byte 0xef
+tdat3:  .byte 0xef
+tdat4:  .byte 0xef
+tdat5:  .byte 0xef
+tdat6:  .byte 0xef
+tdat7:  .byte 0xef
+tdat8:  .byte 0xef
+tdat9:  .byte 0xef
+tdat10: .byte 0xef
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sd.S b/isa/rv64ui/sd.S
new file mode 100644
index 0000000..6f6cb45
--- /dev/null
+++ b/isa/rv64ui/sd.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# sd.S
+#-----------------------------------------------------------------------------
+#
+# Test sd instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0,  tdat );
+  TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8,  tdat );
+  TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16,  tdat );
+  TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 );
+  TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 );
+  TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8,  tdat8 );
+  TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0,   tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x1234567812345678, \
+    la  x1, tdat9; \
+    li  x2, 0x1234567812345678; \
+    addi x4, x1, -32; \
+    sd x2, 32(x4); \
+    ld x3, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x5821309858213098, \
+    la  x1, tdat9; \
+    li  x2, 0x5821309858213098; \
+    addi x1, x1, -3; \
+    sd x2, 11(x1); \
+    la  x4, tdat10; \
+    ld x3, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .dword 0xdeadbeefdeadbeef
+tdat2:  .dword 0xdeadbeefdeadbeef
+tdat3:  .dword 0xdeadbeefdeadbeef
+tdat4:  .dword 0xdeadbeefdeadbeef
+tdat5:  .dword 0xdeadbeefdeadbeef
+tdat6:  .dword 0xdeadbeefdeadbeef
+tdat7:  .dword 0xdeadbeefdeadbeef
+tdat8:  .dword 0xdeadbeefdeadbeef
+tdat9:  .dword 0xdeadbeefdeadbeef
+tdat10: .dword 0xdeadbeefdeadbeef
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sh.S b/isa/rv64ui/sh.S
new file mode 100644
index 0000000..e68f31a
--- /dev/null
+++ b/isa/rv64ui/sh.S
@@ -0,0 +1,100 @@
+#*****************************************************************************
+# sh.S
+#-----------------------------------------------------------------------------
+#
+# Test sh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat );
+  TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat );
+#ifdef __RISCVEL
+  TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat );
+#elif defined(__RISCVEB)
+#else
+  TEST_ST_OP( 4, lw, sh, 0x000000000aa0beef, 4, tdat );
+#error unknown endianness!
+#endif
+  TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 );
+  TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 );
+  TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 );
+  TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0,  tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x5678, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sh x2, 32(x4); \
+    lh x3, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x3098, \
+    la  x1, tdat9; \
+    li  x2, 0x00003098; \
+    addi x1, x1, -5; \
+    sh x2, 7(x1); \
+    la  x4, tdat10; \
+    lh x3, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4,  tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4,  tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
+
+  li a0, 0xbeef
+  la a1, tdat
+  sh a0, 6(a1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0xbeef
+tdat2:  .half 0xbeef
+tdat3:  .half 0xbeef
+tdat4:  .half 0xbeef
+tdat5:  .half 0xbeef
+tdat6:  .half 0xbeef
+tdat7:  .half 0xbeef
+tdat8:  .half 0xbeef
+tdat9:  .half 0xbeef
+tdat10: .half 0xbeef
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/simple.S b/isa/rv64ui/simple.S
new file mode 100644
index 0000000..a667035
--- /dev/null
+++ b/isa/rv64ui/simple.S
@@ -0,0 +1,25 @@
+#*****************************************************************************
+# simple.S
+#-----------------------------------------------------------------------------
+#
+# This is the most basic self checking test. If your simulator does not
+# pass thiss then there is little chance that it will pass any of the
+# more complicated self checking tests.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sll.S b/isa/rv64ui/sll.S
new file mode 100644
index 0000000..935da3d
--- /dev/null
+++ b/isa/rv64ui/sll.S
@@ -0,0 +1,88 @@
+#*****************************************************************************
+# sll.S
+#-----------------------------------------------------------------------------
+#
+# Test sll instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sll, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_RR_OP( 3,  sll, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_RR_OP( 4,  sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_OP( 5,  sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_OP( 6,  sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_OP( 7,  sll, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_RR_OP( 8,  sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_RR_OP( 9,  sll, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7  );
+  TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 );
+  TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom six bits
+
+  TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
+  TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 );
+  TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 );
+  TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce );
+  TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sll, 0 );
+  TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/slli.S b/isa/rv64ui/slli.S
new file mode 100644
index 0000000..aeb5ce9
--- /dev/null
+++ b/isa/rv64ui/slli.S
@@ -0,0 +1,66 @@
+#*****************************************************************************
+# slli.S
+#-----------------------------------------------------------------------------
+#
+# Test slli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slli, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_IMM_OP( 3,  slli, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_IMM_OP( 4,  slli, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_OP( 5,  slli, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_OP( 6,  slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_OP( 7,  slli, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  slli, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, slli, 0, 32 );
+  TEST_IMM_ZERODEST( 25, slli, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/slliw.S b/isa/rv64ui/slliw.S
new file mode 100644
index 0000000..7cc7c41
--- /dev/null
+++ b/isa/rv64ui/slliw.S
@@ -0,0 +1,66 @@
+#*****************************************************************************
+# slliw.S
+#-----------------------------------------------------------------------------
+#
+# Test slliw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slliw, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_IMM_OP( 3,  slliw, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_IMM_OP( 4,  slliw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_OP( 5,  slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_OP( 6,  slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_OP( 7,  slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 );
+  TEST_IMM_ZERODEST( 25, slliw, 31, 28 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sllw.S b/isa/rv64ui/sllw.S
new file mode 100644
index 0000000..4663be3
--- /dev/null
+++ b/isa/rv64ui/sllw.S
@@ -0,0 +1,88 @@
+#*****************************************************************************
+# sllw.S
+#-----------------------------------------------------------------------------
+#
+# Test sllw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sllw, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_RR_OP( 3,  sllw, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_RR_OP( 4,  sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_OP( 5,  sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_OP( 6,  sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_OP( 7,  sllw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_RR_OP( 8,  sllw, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_RR_OP( 9,  sllw, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_RR_OP( 10, sllw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_RR_OP( 11, sllw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_RR_OP( 12, sllw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_RR_OP( 13, sllw, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_RR_OP( 14, sllw, 0xffffffff90909080, 0x0000000021212121, 7  );
+  TEST_RR_OP( 15, sllw, 0x0000000048484000, 0x0000000021212121, 14 );
+  TEST_RR_OP( 16, sllw, 0xffffffff80000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, sllw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
+  TEST_RR_OP( 18, sllw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 );
+  TEST_RR_OP( 19, sllw, 0xffffffff90909080, 0x0000000021212121, 0xffffffffffffffe7 );
+  TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee );
+  TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sllw, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sllw, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sllw, 24, 3 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sllw, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sllw, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sllw, 0 );
+  TEST_RR_ZERODEST( 43, sllw, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/slt.S b/isa/rv64ui/slt.S
new file mode 100644
index 0000000..ee3203a
--- /dev/null
+++ b/isa/rv64ui/slt.S
@@ -0,0 +1,82 @@
+#*****************************************************************************
+# slt.S
+#-----------------------------------------------------------------------------
+#
+# Test slt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  slt, 0, 0x0000000000000000, 0x0000000000000000 );
+  TEST_RR_OP( 3,  slt, 0, 0x0000000000000001, 0x0000000000000001 );
+  TEST_RR_OP( 4,  slt, 1, 0x0000000000000003, 0x0000000000000007 );
+  TEST_RR_OP( 5,  slt, 0, 0x0000000000000007, 0x0000000000000003 );
+
+  TEST_RR_OP( 6,  slt, 0, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 7,  slt, 1, 0xffffffff80000000, 0x0000000000000000 );
+  TEST_RR_OP( 8,  slt, 1, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 9,  slt, 1, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
+  TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
+  TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
+  TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
+  TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1,  9, 13 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1,  8, 13 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1,  7, 13 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1,  6, 13 );
+
+  TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
+  TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
+  TEST_RR_ZEROSRC12( 37, slt, 0 );
+  TEST_RR_ZERODEST( 38, slt, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/slti.S b/isa/rv64ui/slti.S
new file mode 100644
index 0000000..77dc52c
--- /dev/null
+++ b/isa/rv64ui/slti.S
@@ -0,0 +1,68 @@
+#*****************************************************************************
+# slti.S
+#-----------------------------------------------------------------------------
+#
+# Test slti instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slti, 0, 0x0000000000000000, 0x000 );
+  TEST_IMM_OP( 3,  slti, 0, 0x0000000000000001, 0x001 );
+  TEST_IMM_OP( 4,  slti, 1, 0x0000000000000003, 0x007 );
+  TEST_IMM_OP( 5,  slti, 0, 0x0000000000000007, 0x003 );
+
+  TEST_IMM_OP( 6,  slti, 0, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 7,  slti, 1, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 8,  slti, 1, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 9,  slti, 1, 0x0000000000000000, 0x7ff );
+  TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 );
+  TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff );
+
+  TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
+  TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17,  8 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
+
+  TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
+  TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sltiu.S b/isa/rv64ui/sltiu.S
new file mode 100644
index 0000000..0617e38
--- /dev/null
+++ b/isa/rv64ui/sltiu.S
@@ -0,0 +1,68 @@
+#*****************************************************************************
+# sltiu.S
+#-----------------------------------------------------------------------------
+#
+# Test sltiu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  sltiu, 0, 0x0000000000000000, 0x000 );
+  TEST_IMM_OP( 3,  sltiu, 0, 0x0000000000000001, 0x001 );
+  TEST_IMM_OP( 4,  sltiu, 1, 0x0000000000000003, 0x007 );
+  TEST_IMM_OP( 5,  sltiu, 0, 0x0000000000000007, 0x003 );
+
+  TEST_IMM_OP( 6,  sltiu, 1, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 7,  sltiu, 0, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 8,  sltiu, 1, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 9,  sltiu, 1, 0x0000000000000000, 0x7ff );
+  TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 );
+  TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff );
+
+  TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 );
+  TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 );
+  TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17,  8 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 );
+
+  TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff );
+  TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sltu.S b/isa/rv64ui/sltu.S
new file mode 100644
index 0000000..f853d95
--- /dev/null
+++ b/isa/rv64ui/sltu.S
@@ -0,0 +1,82 @@
+#*****************************************************************************
+# sltu.S
+#-----------------------------------------------------------------------------
+#
+# Test sltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sltu, 0, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sltu, 0, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sltu, 1, 0x00000003, 0x00000007 );
+  TEST_RR_OP( 5,  sltu, 0, 0x00000007, 0x00000003 );
+
+  TEST_RR_OP( 6,  sltu, 1, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 7,  sltu, 0, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 8,  sltu, 1, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 9,  sltu, 1, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 );
+  TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 );
+  TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 );
+  TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 );
+  TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1,  9, 13 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1,  8, 13 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1,  7, 13 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1,  6, 13 );
+
+  TEST_RR_ZEROSRC1( 35, sltu, 1, -1 );
+  TEST_RR_ZEROSRC2( 36, sltu, 0, -1 );
+  TEST_RR_ZEROSRC12( 37, sltu, 0 );
+  TEST_RR_ZERODEST( 38, sltu, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sra.S b/isa/rv64ui/sra.S
new file mode 100644
index 0000000..2dca12e
--- /dev/null
+++ b/isa/rv64ui/sra.S
@@ -0,0 +1,88 @@
+#*****************************************************************************
+# sra.S
+#-----------------------------------------------------------------------------
+#
+# Test sra instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sra, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_RR_OP( 3,  sra, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_RR_OP( 4,  sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_OP( 5,  sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_OP( 6,  sra, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_RR_OP( 7,  sra, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_RR_OP( 8,  sra, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_RR_OP( 9,  sra, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 );
+  TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 );
+  TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 );
+  TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce );
+  TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sra, 0 );
+  TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/srai.S b/isa/rv64ui/srai.S
new file mode 100644
index 0000000..4923254
--- /dev/null
+++ b/isa/rv64ui/srai.S
@@ -0,0 +1,66 @@
+#*****************************************************************************
+# srai.S
+#-----------------------------------------------------------------------------
+#
+# Test srai instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  srai, 0xffffff8000000000, 0xffffff8000000000, 0  );
+  TEST_IMM_OP( 3,  srai, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_IMM_OP( 4,  srai, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_OP( 5,  srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_OP( 6,  srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_OP( 7,  srai, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_IMM_OP( 8,  srai, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_IMM_OP( 9,  srai, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, srai, 0, 32 );
+  TEST_IMM_ZERODEST( 25, srai, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sraiw.S b/isa/rv64ui/sraiw.S
new file mode 100644
index 0000000..a66f81b
--- /dev/null
+++ b/isa/rv64ui/sraiw.S
@@ -0,0 +1,69 @@
+#*****************************************************************************
+# sraiw.S
+#-----------------------------------------------------------------------------
+#
+# Test sraiw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  sraiw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_IMM_OP( 3,  sraiw, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_IMM_OP( 4,  sraiw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_OP( 5,  sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_OP( 6,  sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_OP( 7,  sraiw, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_IMM_OP( 8,  sraiw, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_IMM_OP( 9,  sraiw, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_IMM_OP( 10, sraiw, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_IMM_OP( 11, sraiw, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_IMM_OP( 12, sraiw, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_IMM_OP( 13, sraiw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_IMM_OP( 14, sraiw, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, sraiw, 0, 31 );
+  TEST_IMM_ZERODEST( 25, sraiw, 31, 28 );
+
+  TEST_IMM_OP( 26, sraiw, 0x0000000000000000, 0x00e0000000000000, 28)
+  TEST_IMM_OP( 27, sraiw, 0xffffffffff000000, 0x00000000f0000000, 4)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sraw.S b/isa/rv64ui/sraw.S
new file mode 100644
index 0000000..e6a2951
--- /dev/null
+++ b/isa/rv64ui/sraw.S
@@ -0,0 +1,88 @@
+#*****************************************************************************
+# sraw.S
+#-----------------------------------------------------------------------------
+#
+# Test sraw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sraw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_RR_OP( 3,  sraw, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_RR_OP( 4,  sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_OP( 5,  sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_OP( 6,  sraw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_RR_OP( 7,  sraw, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_RR_OP( 8,  sraw, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_RR_OP( 9,  sraw, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_RR_OP( 10, sraw, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_RR_OP( 11, sraw, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_RR_OP( 12, sraw, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_RR_OP( 13, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_RR_OP( 14, sraw, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_RR_OP( 15, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_RR_OP( 16, sraw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, sraw, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffe0 );
+  TEST_RR_OP( 18, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffe1 );
+  TEST_RR_OP( 19, sraw, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffe7 );
+  TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee );
+  TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sraw, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sraw, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sraw, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sraw, 0 );
+  TEST_RR_ZERODEST( 43, sraw, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/srl.S b/isa/rv64ui/srl.S
new file mode 100644
index 0000000..2087b90
--- /dev/null
+++ b/isa/rv64ui/srl.S
@@ -0,0 +1,88 @@
+#*****************************************************************************
+# srl.S
+#-----------------------------------------------------------------------------
+#
+# Test srl instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  srl, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_RR_OP( 3,  srl, 0x7fffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_RR_OP( 4,  srl, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_OP( 5,  srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_OP( 6,  srl, 0x00000001ffffffff, 0xffffffff80000001, 31 );
+
+  TEST_RR_OP( 7,  srl, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_RR_OP( 8,  srl, 0x7fffffffffffffff, 0xffffffffffffffff, 1  );
+  TEST_RR_OP( 9,  srl, 0x01ffffffffffffff, 0xffffffffffffffff, 7  );
+  TEST_RR_OP( 10, srl, 0x0003ffffffffffff, 0xffffffffffffffff, 14 );
+  TEST_RR_OP( 11, srl, 0x00000001ffffffff, 0xffffffffffffffff, 31 );
+
+  TEST_RR_OP( 12, srl, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_RR_OP( 13, srl, 0x0000000010909090, 0x0000000021212121, 1  );
+  TEST_RR_OP( 14, srl, 0x0000000000424242, 0x0000000021212121, 7  );
+  TEST_RR_OP( 15, srl, 0x0000000000008484, 0x0000000021212121, 14 );
+  TEST_RR_OP( 16, srl, 0x0000000000000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
+  TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
+  TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
+  TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
+  TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, srl, 0 );
+  TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/srli.S b/isa/rv64ui/srli.S
new file mode 100644
index 0000000..755db14
--- /dev/null
+++ b/isa/rv64ui/srli.S
@@ -0,0 +1,66 @@
+#*****************************************************************************
+# srli.S
+#-----------------------------------------------------------------------------
+#
+# Test srli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  srli, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_IMM_OP( 3,  srli, 0x7fffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_IMM_OP( 4,  srli, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_OP( 5,  srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_OP( 6,  srli, 0x00000001ffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_OP( 7,  srli, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  srli, 0x7fffffffffffffff, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  srli, 0x01ffffffffffffff, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, srli, 0x0003ffffffffffff, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, srli, 0x00000001ffffffff, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, srli, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, srli, 0x0000000010909090, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, srli, 0x0000000000424242, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, srli, 0x0000000000008484, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, srli, 0x0000000000000000, 0x0000000021212121, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01ffffffff000000, 0xffffffff80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001ffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01ffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001ffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, srli, 0, 32 );
+  TEST_IMM_ZERODEST( 25, srli, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/srliw.S b/isa/rv64ui/srliw.S
new file mode 100644
index 0000000..d4159d1
--- /dev/null
+++ b/isa/rv64ui/srliw.S
@@ -0,0 +1,66 @@
+#*****************************************************************************
+# srliw.S
+#-----------------------------------------------------------------------------
+#
+# Test srliw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  srliw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_IMM_OP( 3,  srliw, 0x0000000040000000, 0xffffffff80000000, 1  );
+  TEST_IMM_OP( 4,  srliw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_IMM_OP( 5,  srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_IMM_OP( 6,  srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_IMM_OP( 7,  srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  srliw, 0x000000007fffffff, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 );
+  TEST_IMM_ZERODEST( 25, srliw, 31, 28 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/srlw.S b/isa/rv64ui/srlw.S
new file mode 100644
index 0000000..d103611
--- /dev/null
+++ b/isa/rv64ui/srlw.S
@@ -0,0 +1,88 @@
+#*****************************************************************************
+# srlw.S
+#-----------------------------------------------------------------------------
+#
+# Test srlw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  srlw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_RR_OP( 3,  srlw, 0x0000000040000000, 0xffffffff80000000, 1  );
+  TEST_RR_OP( 4,  srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_OP( 5,  srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_OP( 6,  srlw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_RR_OP( 7,  srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_RR_OP( 8,  srlw, 0x000000007fffffff, 0xffffffffffffffff, 1  );
+  TEST_RR_OP( 9,  srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7  );
+  TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
+  TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 );
+
+  TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1  );
+  TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7  );
+  TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 );
+  TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
+  TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 );
+  TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 );
+  TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee );
+  TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, srlw, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, srlw, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, srlw, 0 );
+  TEST_RR_ZERODEST( 43, srlw, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sub.S b/isa/rv64ui/sub.S
new file mode 100644
index 0000000..7180e08
--- /dev/null
+++ b/isa/rv64ui/sub.S
@@ -0,0 +1,81 @@
+#*****************************************************************************
+# sub.S
+#-----------------------------------------------------------------------------
+#
+# Test sub instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
+  TEST_RR_OP( 3,  sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
+  TEST_RR_OP( 4,  sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
+
+  TEST_RR_OP( 5,  sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
+  TEST_RR_OP( 7,  sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
+  TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
+  TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
+  TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
+  TEST_RR_ZEROSRC12( 36, sub, 0 );
+  TEST_RR_ZERODEST( 37, sub, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/subw.S b/isa/rv64ui/subw.S
new file mode 100644
index 0000000..b54f608
--- /dev/null
+++ b/isa/rv64ui/subw.S
@@ -0,0 +1,81 @@
+#*****************************************************************************
+# subw.S
+#-----------------------------------------------------------------------------
+#
+# Test subw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  subw, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
+  TEST_RR_OP( 3,  subw, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
+  TEST_RR_OP( 4,  subw, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
+
+  TEST_RR_OP( 5,  subw, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  subw, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
+  TEST_RR_OP( 7,  subw, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  subw, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  subw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, subw, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, subw, 0x000000007fff8001, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, subw, 0xffffffff80007fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, subw, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, subw, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, subw, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 16, subw, 2, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 17, subw, 3, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 18, subw, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 19, 0, subw, 2, 13, 11 );
+  TEST_RR_DEST_BYPASS( 20, 1, subw, 3, 14, 11 );
+  TEST_RR_DEST_BYPASS( 21, 2, subw, 4, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 22, 0, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 23, 0, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 2, subw, 4, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 1, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 2, 0, subw, 4, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 28, 0, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 29, 0, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 2, subw, 4, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 1, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 2, 0, subw, 4, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 34, subw, 15, -15 );
+  TEST_RR_ZEROSRC2( 35, subw, 32, 32 );
+  TEST_RR_ZEROSRC12( 36, subw, 0 );
+  TEST_RR_ZERODEST( 37, subw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/sw.S b/isa/rv64ui/sw.S
new file mode 100644
index 0000000..a6f2b50
--- /dev/null
+++ b/isa/rv64ui/sw.S
@@ -0,0 +1,90 @@
+#*****************************************************************************
+# sw.S
+#-----------------------------------------------------------------------------
+#
+# Test sw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0,  tdat );
+  TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4,  tdat );
+  TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8,  tdat );
+  TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 );
+  TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8,  tdat8 );
+  TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4,  tdat8 );
+  TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0,   tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x12345678, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sw x2, 32(x4); \
+    lw x3, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x58213098, \
+    la  x1, tdat9; \
+    li  x2, 0x58213098; \
+    addi x1, x1, -3; \
+    sw x2, 7(x1); \
+    la  x4, tdat10; \
+    lw x3, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8,  tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8,  tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0xdeadbeef
+tdat2:  .word 0xdeadbeef
+tdat3:  .word 0xdeadbeef
+tdat4:  .word 0xdeadbeef
+tdat5:  .word 0xdeadbeef
+tdat6:  .word 0xdeadbeef
+tdat7:  .word 0xdeadbeef
+tdat8:  .word 0xdeadbeef
+tdat9:  .word 0xdeadbeef
+tdat10: .word 0xdeadbeef
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/xor.S b/isa/rv64ui/xor.S
new file mode 100644
index 0000000..172a15a
--- /dev/null
+++ b/isa/rv64ui/xor.S
@@ -0,0 +1,67 @@
+#*****************************************************************************
+# xor.S
+#-----------------------------------------------------------------------------
+#
+# Test xor instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, xor, 0 );
+  TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64ui/xori.S b/isa/rv64ui/xori.S
new file mode 100644
index 0000000..4f95ea7
--- /dev/null
+++ b/isa/rv64ui/xori.S
@@ -0,0 +1,53 @@
+#*****************************************************************************
+# xori.S
+#-----------------------------------------------------------------------------
+#
+# Test xori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f );
+  TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
+  TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f );
+
+   #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 8,  1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
+  TEST_IMM_DEST_BYPASS( 9,  2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f );
+  TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/Makefile b/isa/rv64uv/Makefile
new file mode 100644
index 0000000..1c41cca
--- /dev/null
+++ b/isa/rv64uv/Makefile
@@ -0,0 +1,135 @@
+#=======================================================================
+# Makefile for riscv-tests
+#-----------------------------------------------------------------------
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+rv64uv_sc_tests = \
+	wakeup fence \
+	vvcfgivl vvcfg vsetvl \
+	vfmvv vmsv vmvv \
+	utidx \
+	lb lbu lh lhu lw lwu ld \
+	sb sh sw sd \
+	fld flw \
+	fsd fsw \
+	amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoswap_d \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
+	imul \
+	movn movz \
+	fcvt fma \
+	fmovn fmovz \
+	vvadd_d vvadd_w vvadd_fd vvadd_fw \
+	vvmul_d \
+	vvadd_branch \
+
+rv64uv_mc_tests = \
+
+rv64uv_sc_vec_tests = \
+	beq bge bgeu blt bltu bne \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss
+RISCV_SIM = riscv-isa-run
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.hex: %
+	elf2hex 16 16384 $< > $@
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) $< 2> $@
+
+rv64uv_p_tests_bin = $(addprefix rv64uv-p-, $(rv64uv_sc_tests))
+rv64uv_p_tests_dump = $(addsuffix .dump, $(rv64uv_p_tests_bin))
+rv64uv_p_tests_hex = $(addsuffix .hex, $(rv64uv_p_tests_bin))
+rv64uv_p_tests_out  = $(addsuffix .out,  $(rv64uv_p_tests_bin))
+
+$(rv64uv_p_tests_bin): rv64uv-p-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/scalar -T../../env/p/link.ld $< -o $@
+
+rv64uv_pm_tests_bin = $(addprefix rv64uv-pm-, $(rv64uv_mc_tests))
+rv64uv_pm_tests_dump = $(addsuffix .dump, $(rv64uv_pm_tests_bin))
+rv64uv_pm_tests_hex = $(addsuffix .hex, $(rv64uv_pm_tests_bin))
+rv64uv_pm_tests_out  = $(addsuffix .out,  $(rv64uv_pm_tests_bin))
+
+$(rv64uv_pm_tests_bin): rv64uv-pm-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pm -I../macros/scalar -T../../env/pm/link.ld $< -o $@
+
+rv64uv_v_tests_bin = $(addprefix rv64uv-v-, $(rv64uv_sc_tests))
+rv64uv_v_tests_dump = $(addsuffix .dump, $(rv64uv_v_tests_bin))
+rv64uv_v_tests_hex = $(addsuffix .hex, $(rv64uv_v_tests_bin))
+rv64uv_v_tests_out  = $(addsuffix .out,  $(rv64uv_v_tests_bin))
+
+$(rv64uv_v_tests_bin): rv64uv-v-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -std=gnu99 -O2 -I../../env/v -I../macros/scalar -T../../env/v/link.ld ../../env/v/entry.S ../../env/v/vm.c $< -lc -o $@
+
+rv64uv_p_vec_tests_bin = $(addprefix rv64uv-p-vec-, $(rv64uv_sc_vec_tests))
+rv64uv_p_vec_tests_dump = $(addsuffix .dump, $(rv64uv_p_vec_tests_bin))
+rv64uv_p_vec_tests_hex = $(addsuffix .hex, $(rv64uv_p_vec_tests_bin))
+rv64uv_p_vec_tests_out  = $(addsuffix .out,  $(rv64uv_p_vec_tests_bin))
+
+$(rv64uv_p_vec_tests_bin): rv64uv-p-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/vector -T../../env/p/link.ld $< -o $@
+
+rv64uv_pt_vec_tests_bin = $(addprefix rv64uv-pt-vec-, $(rv64uv_sc_vec_tests))
+rv64uv_pt_vec_tests_dump = $(addsuffix .dump, $(rv64uv_pt_vec_tests_bin))
+rv64uv_pt_vec_tests_hex = $(addsuffix .hex, $(rv64uv_pt_vec_tests_bin))
+rv64uv_pt_vec_tests_out  = $(addsuffix .out,  $(rv64uv_pt_vec_tests_bin))
+
+$(rv64uv_pt_vec_tests_bin): rv64uv-pt-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pt -I../macros/vector -T../../env/pt/link.ld $< -o $@
+
+rv64uv_v_vec_tests_bin = $(addprefix rv64uv-v-vec-, $(rv64uv_sc_vec_tests))
+rv64uv_v_vec_tests_dump = $(addsuffix .dump, $(rv64uv_v_vec_tests_bin))
+rv64uv_v_vec_tests_hex = $(addsuffix .hex, $(rv64uv_v_vec_tests_bin))
+rv64uv_v_vec_tests_out  = $(addsuffix .out,  $(rv64uv_v_vec_tests_bin))
+
+$(rv64uv_v_vec_tests_bin): rv64uv-v-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -std=gnu99 -O2 -I../../env/v -I../macros/vector -T../../env/v/link.ld ../../env/v/entry.S ../../env/v/vm.c $< -lc -o $@
+
+riscv-: \
+	$(rv64uv_p_tests_dump) $(rv64uv_p_tests_hex) \
+	$(rv64uv_pm_tests_dump) $(rv64uv_pm_tests_hex) \
+	$(rv64uv_v_tests_dump) $(rv64uv_v_tests_hex) \
+	$(rv64uv_p_vec_tests_dump) $(rv64uv_p_vec_tests_hex) \
+	$(rv64uv_pt_vec_tests_dump) $(rv64uv_pt_vec_tests_hex) \
+	$(rv64uv_v_vec_tests_dump) $(rv64uv_v_vec_tests_hex) \
+
+out = $(rv64uv_p_tests_out) $(rv64uv_pm_tests_out)
+
+run: $(out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(out); echo;
+
+junk += \
+  $(rv64uv_p_tests_bin) $(rv64uv_p_tests_dump) $(rv64uv_p_tests_hex) $(rv64uv_p_tests_out) \
+  $(rv64uv_pm_tests_bin) $(rv64uv_pm_tests_dump) $(rv64uv_pm_tests_hex) $(rv64uv_pm_tests_out) \
+  $(rv64uv_v_tests_bin) $(rv64uv_v_tests_dump) $(rv64uv_v_tests_hex) $(rv64uv_v_tests_out) \
+  $(rv64uv_p_vec_tests_bin) $(rv64uv_p_vec_tests_dump) $(rv64uv_p_vec_tests_hex) $(rv64uv_p_vec_tests_out) \
+  $(rv64uv_pt_vec_tests_bin) $(rv64uv_pt_vec_tests_dump) $(rv64uv_pt_vec_tests_hex) $(rv64uv_pt_vec_tests_out) \
+  $(rv64uv_v_vec_tests_bin) $(rv64uv_v_vec_tests_dump) $(rv64uv_v_vec_tests_hex) $(rv64uv_v_vec_tests_out) \
+
+#------------------------------------------------------------
+# Default
+
+all: riscv-
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S
new file mode 100644
index 0000000..053f791
--- /dev/null
+++ b/isa/rv64uv/amoadd_d.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoadd_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  li a5,1
+  vmsv vx3,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+loop:
+  ld a0,0(a6)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a6,a6,8
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  amoadd.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .dword 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amoadd_w.S b/isa/rv64uv/amoadd_w.S
new file mode 100644
index 0000000..cf006a7
--- /dev/null
+++ b/isa/rv64uv/amoadd_w.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  li a5,1
+  vmsv vx3,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  amoadd.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amoand_d.S b/isa/rv64uv/amoand_d.S
new file mode 100644
index 0000000..5167ce6
--- /dev/null
+++ b/isa/rv64uv/amoand_d.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoand_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,0
+loop:
+  ld a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,8
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  li x3,-1
+  amoand.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .dword 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amoand_w.S b/isa/rv64uv/amoand_w.S
new file mode 100644
index 0000000..111291b
--- /dev/null
+++ b/isa/rv64uv/amoand_w.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoand_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,0
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  li x3,-1
+  amoand.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amomax_d.S b/isa/rv64uv/amomax_d.S
new file mode 100644
index 0000000..e29e6e7
--- /dev/null
+++ b/isa/rv64uv/amomax_d.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,0
+loop:
+  ld a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,8
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amomax.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .dword 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S
new file mode 100644
index 0000000..2f7ebf4
--- /dev/null
+++ b/isa/rv64uv/amomax_w.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# amomax_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,0
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amomax.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amomaxu_d.S b/isa/rv64uv/amomaxu_d.S
new file mode 100644
index 0000000..59a8a28
--- /dev/null
+++ b/isa/rv64uv/amomaxu_d.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  ld a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,8
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amomaxu.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .dword -1
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amomaxu_w.S b/isa/rv64uv/amomaxu_w.S
new file mode 100644
index 0000000..2a97c71
--- /dev/null
+++ b/isa/rv64uv/amomaxu_w.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# amomaxu_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amomaxu.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word -1
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S
new file mode 100644
index 0000000..01e1feb
--- /dev/null
+++ b/isa/rv64uv/amomin_d.S
@@ -0,0 +1,62 @@
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  ld a0,0(a5)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a5,a5,8
+  addi a1,a1,1
+  addi a2,a2,-1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3, x3, 3
+  add x2, x2, x3
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amomin.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .skip 16384
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amomin_w.S b/isa/rv64uv/amomin_w.S
new file mode 100644
index 0000000..bac8400
--- /dev/null
+++ b/isa/rv64uv/amomin_w.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# amomin_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,0
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  addi a2,a2,-1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amomin.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amominu_d.S b/isa/rv64uv/amominu_d.S
new file mode 100644
index 0000000..0951bab
--- /dev/null
+++ b/isa/rv64uv/amominu_d.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,0
+loop:
+  ld a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,8
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amominu.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .dword 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S
new file mode 100644
index 0000000..67e5f93
--- /dev/null
+++ b/isa/rv64uv/amominu_w.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# amominu_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,0
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  li x1,-1
+  mul x3,x3,x1
+  amominu.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S
new file mode 100644
index 0000000..b26f963
--- /dev/null
+++ b/isa/rv64uv/amoor_d.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  ld a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,8
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  li x3,7
+  amoor.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .dword -1
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
new file mode 100644
index 0000000..4d18c10
--- /dev/null
+++ b/isa/rv64uv/amoor_w.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoor_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a2,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  li x3,7
+  amoor.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word -1
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amoswap_d.S b/isa/rv64uv/amoswap_d.S
new file mode 100644
index 0000000..0858277
--- /dev/null
+++ b/isa/rv64uv/amoswap_d.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoswap_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.d instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a1,0
+loop:
+  ld a0,0(a6)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a6,a6,8
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  amoswap.d x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .dword 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/amoswap_w.S b/isa/rv64uv/amoswap_w.S
new file mode 100644
index 0000000..ae6f1da
--- /dev/null
+++ b/isa/rv64uv/amoswap_w.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,0
+
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsw vx1,a6
+  fence.v.l
+
+  li a1,0
+loop:
+  lw a0,0(a6)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a6,a6,4
+  addi a1,a1,1
+  bne a1,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  addi x3,x3,1
+  amoswap.w x1,x3,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+amodest:
+  .word 0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/beq.S b/isa/rv64uv/beq.S
new file mode 100644
index 0000000..aa6f2ff
--- /dev/null
+++ b/isa/rv64uv/beq.S
@@ -0,0 +1,94 @@
+#*****************************************************************************
+# beq.S
+#-----------------------------------------------------------------------------
+#
+# Test beq instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, beq,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, beq,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, beq,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN( 6, beq,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, beq, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, beq,  1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test when uts diverge
+  #-------------------------------------------------------------
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 24, beq, 1, 1, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 25, beq, 2, 2, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 26, beq, 3, 3, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 27, beq, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 28, beq, 2, 400, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 29, beq, 3, 163216, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  
+  TEST_BR2_DIVERGED_FULL12( 30, beq, 1, 1, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_FULL12( 31, beq, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+
+  TEST_BR2_DIVERGED_MEM_FULL12( 32, beq, 1);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/bge.S b/isa/rv64uv/bge.S
new file mode 100644
index 0000000..06d15de
--- /dev/null
+++ b/isa/rv64uv/bge.S
@@ -0,0 +1,97 @@
+#*****************************************************************************
+# bge.S
+#-----------------------------------------------------------------------------
+#
+# Test bge instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bge,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, bge,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
+  TEST_BR2_OP_TAKEN( 5, bge,  1,  0 );
+  TEST_BR2_OP_TAKEN( 6, bge,  1, -1 );
+  TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bge,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN(  9, bge, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
+  TEST_BR2_OP_NOTTAKEN( 11, bge, -2,  1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
+
+  #-------------------------------------------------------------
+  # Test when uts diverge
+  #-------------------------------------------------------------
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 24, bge, 1, 1, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 25, bge, 2, 2, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 26, bge, 3, 3, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 27, bge, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 28, bge, 2, 400, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 29, bge, 3, 163216, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  ) 
+ 
+  TEST_BR2_DIVERGED_FULL12( 30, bge, 1, 1, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_FULL12( 31, bge, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+
+  TEST_BR2_DIVERGED_MEM_FULL12( 32, bge, 1);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/bgeu.S b/isa/rv64uv/bgeu.S
new file mode 100644
index 0000000..5f54670
--- /dev/null
+++ b/isa/rv64uv/bgeu.S
@@ -0,0 +1,97 @@
+#*****************************************************************************
+# bgeu.S
+#-----------------------------------------------------------------------------
+#
+# Test bgeu instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bgeu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_NOTTAKEN(  9, bgeu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  #-------------------------------------------------------------
+  # Test when uts diverge
+  #-------------------------------------------------------------
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 24, bgeu, 1, 1, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 25, bgeu, 2, 2, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 26, bgeu, 3, 3, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 27, bgeu, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 28, bgeu, 2, 400, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 29, bgeu, 3, 163216, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )        
+
+  TEST_BR2_DIVERGED_FULL12( 30, bgeu, 1, 1, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_FULL12( 31, bgeu, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+
+  TEST_BR2_DIVERGED_MEM_FULL12( 32, bgeu, 1);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/blt.S b/isa/rv64uv/blt.S
new file mode 100644
index 0000000..913c55f
--- /dev/null
+++ b/isa/rv64uv/blt.S
@@ -0,0 +1,94 @@
+#*****************************************************************************
+# blt.S
+#-----------------------------------------------------------------------------
+#
+# Test blt instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, blt,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, blt, -1,  1 );
+  TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, blt,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 6, blt,  1, -1 );
+  TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
+  TEST_BR2_OP_NOTTAKEN( 8, blt,  1, -2 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test when uts diverge
+  #-------------------------------------------------------------
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 24, blt, 1, 1, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 25, blt, 2, 2, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 26, blt, 3, 3, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 27, blt, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 28, blt, 2, 400, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 29, blt, 3, 163216, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  
+  TEST_BR2_DIVERGED_FULL21( 30, blt, 0, 1, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_FULL21( 31, blt, 0, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+
+  TEST_BR2_DIVERGED_MEM_FULL21( 32, blt, 0);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/bltu.S b/isa/rv64uv/bltu.S
new file mode 100644
index 0000000..5629791
--- /dev/null
+++ b/isa/rv64uv/bltu.S
@@ -0,0 +1,94 @@
+#*****************************************************************************
+# bltu.S
+#-----------------------------------------------------------------------------
+#
+# Test bltu instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
+
+  TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  #-------------------------------------------------------------
+  # Test when uts diverge
+  #-------------------------------------------------------------
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 24, bltu, 1, 1, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 25, bltu, 2, 2, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 26, bltu, 3, 3, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 27, bltu, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 28, bltu, 2, 400, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 29, bltu, 3, 163216, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  
+  TEST_BR2_DIVERGED_FULL21( 30, bltu, 0, 1, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_FULL21( 31, bltu, 0, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+
+  TEST_BR2_DIVERGED_MEM_FULL21( 32, bltu, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/bne.S b/isa/rv64uv/bne.S
new file mode 100644
index 0000000..a6b2347
--- /dev/null
+++ b/isa/rv64uv/bne.S
@@ -0,0 +1,94 @@
+#*****************************************************************************
+# bne.S
+#-----------------------------------------------------------------------------
+#
+# Test bne instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bne,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, bne,  1,  0 );
+  TEST_BR2_OP_TAKEN( 4, bne, -1,  1 );
+  TEST_BR2_OP_TAKEN( 5, bne,  1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 6, bne,  0,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, bne,  1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
+
+  #-------------------------------------------------------------
+  # Test when uts diverge
+  #-------------------------------------------------------------
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 24, bne, 1, 1, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 25, bne, 2, 2, \
+    addi x3, x3, 1; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 26, bne, 3, 3, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_ODD_EVEN( 27, bne, 1, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 28, bne, 2, 400, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  TEST_BR2_DIVERGED_ODD_EVEN( 29, bne, 3, 163216, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+  
+  TEST_BR2_DIVERGED_FULL12( 30, bne, 0, 1, \
+    addi x3, x3, 1; \
+  )
+
+  TEST_BR2_DIVERGED_FULL12( 31, bne, 0, 16, \
+    addi x3, x3, 4; \
+    mul x3, x3, x3; \
+  )
+
+  TEST_BR2_DIVERGED_MEM_FULL12( 32, bne, 0);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/data_d.h b/isa/rv64uv/data_d.h
new file mode 100644
index 0000000..9e351af
--- /dev/null
+++ b/isa/rv64uv/data_d.h
@@ -0,0 +1,4096 @@
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diff --git a/isa/rv64uv/fcvt.S b/isa/rv64uv/fcvt.S
new file mode 100644
index 0000000..151e054
--- /dev/null
+++ b/isa/rv64uv/fcvt.S
@@ -0,0 +1,72 @@
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,4
+  vvcfgivl a3,a3,32,32
+
+  la a3,src
+  vld vx2,a3
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a4,dest
+  vfsd vf0,a4
+  fence.v.l
+  la a5,result
+  ld a1,0(a4)
+  ld a2,0(a5)
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a4)
+  ld a2,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a4)
+  ld a2,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a4)
+  ld a2,24(a5)
+  li x28,5
+  bne a1,a2,fail
+  j pass
+
+vtcode:
+  fcvt.d.l f0,x2
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+result:
+  .double 1.0
+  .double 2.0
+  .double 3.0
+  .double 4.0
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/fence.S b/isa/rv64uv/fence.S
new file mode 100644
index 0000000..808fffa
--- /dev/null
+++ b/isa/rv64uv/fence.S
@@ -0,0 +1,54 @@
+#*****************************************************************************
+# fence.S
+#-----------------------------------------------------------------------------
+#
+# Test fence instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  # make sure these don't choke at the beginning
+  fence.v.l
+  fence.v.g
+
+  li a0,1
+  bne a0,x0,skip1
+  fence.v.l
+skip1:
+
+  bne a0,x0,skip3
+  fence.v.g
+skip3:
+
+  j pass
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S
new file mode 100644
index 0000000..ab45100
--- /dev/null
+++ b/isa/rv64uv/fld.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# fld.S
+#-----------------------------------------------------------------------------
+#
+# Test fld instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,4,1
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vfsd vf0,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  addi x28,a2,2
+  ld a1,0(a5)
+  bne a0,a1,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  fld f0,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_fd.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S
new file mode 100644
index 0000000..0a42b7b
--- /dev/null
+++ b/isa/rv64uv/flw.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# flw.S
+#-----------------------------------------------------------------------------
+#
+# Test flw instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,1
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vfsw vf0,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  lw a0,0(a6)
+  addi x28,a2,2
+  lw a1,0(a5)
+  bne a0,a1,fail
+  addi a6,a6,4
+  addi a5,a5,4
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,2
+  add x2,x2,x3
+  flw f0,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_fw.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/fma.S b/isa/rv64uv/fma.S
new file mode 100644
index 0000000..b31136c
--- /dev/null
+++ b/isa/rv64uv/fma.S
@@ -0,0 +1,76 @@
+#*****************************************************************************
+# fma.S
+#-----------------------------------------------------------------------------
+#
+# Test fma instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,2048
+  vvcfgivl a3,a3,3,2
+
+  la a4,src
+  fld f0,0(a4)
+  fld f1,8(a4)
+  mftx.d s0,f0
+  mftx.d s1,f1
+  vmsv vx1,s0
+  vmsv vx2,s1
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+
+  li a7,0
+  li a6,400
+wait:
+  addi a7,a7,1
+  bne a7,a6,wait
+
+  fadd.d f0,f0,f1
+  mftx.d s2,f0
+
+  la a5,dest
+  vfsd vf0,a5
+  fence.v.l
+
+  la s3,result
+  ld s4,0(s3)
+  li x28,2
+  bne s2,s4,fail
+
+  li a2,0
+loop:
+  ld a0,0(a5)
+  addi x28,a2,3
+  bne a0,s4,fail
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a3,loop
+  j pass
+
+vtcode:
+  mxtf.d f0,x1
+  mxtf.d f1,x2
+  fadd.d f0,f0,f1
+  stop
+
+  TEST_PASSFAIL
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+  .double 1.0
+  .double 2.0
+result:
+  .double 3.0
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
new file mode 100644
index 0000000..88ab03c
--- /dev/null
+++ b/isa/rv64uv/fmovn.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# fmovn.S
+#-----------------------------------------------------------------------------
+#
+# Test fmovn instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a6,2048
+  vvcfgivl a6,a6,4,2
+
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a7,dest
+  vfsd vf0,a7
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  ld a0,0(a7)
+  slti a4,a1,10
+  slli a4,a4,63
+  srai a4,a4,63
+  and a5,a2,a4
+  addi x28,a1,2
+  bne a0,a5,fail
+  addi a7,a7,8
+  addi a1,a1,1
+  bne a1,a6,loop
+  j pass
+
+vtcode:
+  utidx x1
+  slti x2,x1,10
+  li x1,-1
+  li x3,0
+  mxtf.d f0,x3
+  mxtf.d f1,x1
+  fmovn f0,x2,f1
+  stop
+
+  TEST_PASSFAIL
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/fmovz.S b/isa/rv64uv/fmovz.S
new file mode 100644
index 0000000..bda56b9
--- /dev/null
+++ b/isa/rv64uv/fmovz.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# fmovz.S
+#-----------------------------------------------------------------------------
+#
+# Test fmovz instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a6,2048
+  vvcfgivl a6,a6,4,2
+
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a7,dest
+  vfsd vf0,a7
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  ld a0,0(a7)
+  slti a4,a1,10
+  slli a4,a4,63
+  srai a4,a4,63
+  xori a4,a4,-1
+  and a5,a2,a4
+  addi x28,a1,2
+  bne a0,a5,fail
+  addi a7,a7,8
+  addi a1,a1,1
+  bne a1,a6,loop
+  j pass
+
+vtcode:
+  utidx x1
+  slti x2,x1,10
+  li x1,-1
+  li x3,0
+  mxtf.d f0,x3
+  mxtf.d f1,x1
+  fmovz f0,x2,f1
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/fsd.S b/isa/rv64uv/fsd.S
new file mode 100644
index 0000000..d85a5f7
--- /dev/null
+++ b/isa/rv64uv/fsd.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# fsd.S
+#-----------------------------------------------------------------------------
+#
+# Test fsd instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,1
+
+  la a5,src
+  vfld vf0,a5
+  la a6,dest
+  vmsv vx2,a6
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  addi x28,a2,2
+  ld a1,0(a5)
+  bne a0,a1,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  fsd f0,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_fd.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S
new file mode 100644
index 0000000..69702d0
--- /dev/null
+++ b/isa/rv64uv/fsw.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# fsw.S
+#-----------------------------------------------------------------------------
+#
+# Test fsw instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,2048
+  vvcfgivl a4,a4,4,1
+
+  la a5,src
+  vflw vf0,a5
+  la a6,dest
+  vmsv vx2,a6
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  fence.v.l
+
+  li a2,0
+loop:
+  lw a0,0(a6)
+  addi x28,a2,2
+  lw a1,0(a5)
+  bne a0,a1,fail
+  addi a6,a6,4
+  addi a5,a5,4
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,2
+  add x2,x2,x3
+  fsw f0,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_fw.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
new file mode 100644
index 0000000..bb9b6a3
--- /dev/null
+++ b/isa/rv64uv/imul.S
@@ -0,0 +1,82 @@
+#*****************************************************************************
+# imul.S
+#-----------------------------------------------------------------------------
+#
+# Test imul instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,2048
+  vvcfgivl a3,a3,3,0
+
+  li a4,20
+  li s0,2
+  vmsv vx1,a4
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  mul s1,a4,s0
+
+  la a5,dest
+  vsd vx1,a5
+  fence.v.l
+
+  li s2,40
+  li x28,2
+  bne s1,s2,fail
+
+  li a1,0
+  li a2,0
+loop:
+  ld a0,0(a5)
+  addi x28,a2,3
+  bne a0,a1,fail
+  addi a5,a5,8
+  addi a1,a1,20
+  addi a2,a2,1
+  bne a2,a3,loop
+  j pass
+
+vtcode:
+  utidx x2
+  mul x1,x2,x1
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/lb.S b/isa/rv64uv/lb.S
new file mode 100644
index 0000000..24c7caa
--- /dev/null
+++ b/isa/rv64uv/lb.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# lb.S
+#-----------------------------------------------------------------------------
+#
+# Test lb instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,56
+  sra a3,a3,56
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  lb x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
new file mode 100644
index 0000000..7fce752
--- /dev/null
+++ b/isa/rv64uv/lbu.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# lbu.S
+#-----------------------------------------------------------------------------
+#
+# Test lby instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,56
+  srl a3,a3,56
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  lbu x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S
new file mode 100644
index 0000000..03303b4
--- /dev/null
+++ b/isa/rv64uv/ld.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# ld.S
+#-----------------------------------------------------------------------------
+#
+# Test ld instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  addi x28,a2,2
+  bne a0,a1,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  ld x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/lh.S b/isa/rv64uv/lh.S
new file mode 100644
index 0000000..98b001c
--- /dev/null
+++ b/isa/rv64uv/lh.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# lh.S
+#-----------------------------------------------------------------------------
+#
+# Test lh instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,48
+  sra a3,a3,48
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  lh x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/lhu.S b/isa/rv64uv/lhu.S
new file mode 100644
index 0000000..caa2c1c
--- /dev/null
+++ b/isa/rv64uv/lhu.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# lhu.S
+#-----------------------------------------------------------------------------
+#
+# Test lhu instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,48
+  srl a3,a3,48
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  lhu x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S
new file mode 100644
index 0000000..5576bc6
--- /dev/null
+++ b/isa/rv64uv/lw.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# lw.S
+#-----------------------------------------------------------------------------
+#
+# Test lw instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,32
+  sra a3,a3,32
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  lw x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S
new file mode 100644
index 0000000..d8b5bf2
--- /dev/null
+++ b/isa/rv64uv/lwu.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# lwu.S
+#-----------------------------------------------------------------------------
+#
+# Test lwu instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a6,dest
+  vsd vx1,a6
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,32
+  srl a3,a3,32
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  lwu x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/movn.S b/isa/rv64uv/movn.S
new file mode 100644
index 0000000..91a5a3c
--- /dev/null
+++ b/isa/rv64uv/movn.S
@@ -0,0 +1,58 @@
+#*****************************************************************************
+# movn.S
+#-----------------------------------------------------------------------------
+#
+# Test movn instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a6,2048
+  vvcfgivl a6,a6,4,0
+
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a7,dest
+  vsd vx3,a7
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  ld a0,0(a7)
+  slt a4,a1,10
+  slli a4,a4,63
+  srai a4,a4,63
+  and a5,a2,a4
+  addi s8,a1,2
+  bne a0,a5,fail
+  addi a7,a7,8
+  addi a1,a1,1
+  bne a1,a6,loop
+  j pass
+
+vtcode:
+  utidx x1
+  slti x2,x1,10
+  li x1,-1
+  li x3,0
+  movn x3,x2,x1
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/movz.S b/isa/rv64uv/movz.S
new file mode 100644
index 0000000..683afdb
--- /dev/null
+++ b/isa/rv64uv/movz.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# movz.S
+#-----------------------------------------------------------------------------
+#
+# Test movz instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a6,2048
+  vvcfgivl a6,a6,4,0
+
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a7,dest
+  vsd vx3,a7
+  fence.v.l
+
+  li a1,0
+  li a2,-1
+loop:
+  ld a0,0(a7)
+  slti a4,a1,10
+  slli a4,a4,63
+  srai a4,a4,63
+  xori a4,a4,-1
+  and a5,a2,a4
+  addi x28,a1,2
+  bne a0,a5,fail
+  addi a7,a7,8
+  addi a1,a1,1
+  bne a1,a6,loop
+  j pass
+
+vtcode:
+  utidx x1
+  slti x2,x1,10
+  li x1,-1
+  li x3,0
+  movz x3,x2,x1
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S
new file mode 100644
index 0000000..bcee091
--- /dev/null
+++ b/isa/rv64uv/sb.S
@@ -0,0 +1,71 @@
+#*****************************************************************************
+# sb.S
+#-----------------------------------------------------------------------------
+#
+# Test sb instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a6,dest
+  li a2,0
+
+initloop:
+  sd x0,0(a6)
+  addi a6,a6,8
+  addi a2,a2,1
+  bne a2,a4,initloop
+  fence
+
+  la a5,src
+  vld vx1,a5
+  la a6,dest
+  vmsv vx2,a6
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,56
+  srl a3,a3,56
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  sb x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S
new file mode 100644
index 0000000..dd6f72a
--- /dev/null
+++ b/isa/rv64uv/sd.S
@@ -0,0 +1,59 @@
+#*****************************************************************************
+# sd.S
+#-----------------------------------------------------------------------------
+#
+# Test sd instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a5,src
+  vld vx1,a5
+  la a6,dest
+  vmsv vx2,a6
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  addi x28,a2,2
+  bne a0,a1,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  sd x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
new file mode 100644
index 0000000..6dc5ab8
--- /dev/null
+++ b/isa/rv64uv/sh.S
@@ -0,0 +1,71 @@
+#*****************************************************************************
+# sh.S
+#-----------------------------------------------------------------------------
+#
+# Test sh instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a6,dest
+  li a2,0
+
+initloop:
+  sd x0,0(a6)
+  addi a6,a6,8
+  addi a2,a2,1
+  bne a2,a4,initloop
+  fence
+
+  la a5,src
+  vld vx1,a5
+  la a6,dest
+  vmsv vx2,a6
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,48
+  srl a3,a3,48
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  sh x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S
new file mode 100644
index 0000000..985e12a
--- /dev/null
+++ b/isa/rv64uv/sw.S
@@ -0,0 +1,71 @@
+#*****************************************************************************
+# sw.S
+#-----------------------------------------------------------------------------
+#
+# Test sw instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a4,512
+  vvcfgivl a4,a4,16,0
+
+  la a6,dest
+  li a2,0
+
+initloop:
+  sd x0,0(a6)
+  addi a6,a6,8
+  addi a2,a2,1
+  bne a2,a4,initloop
+  fence
+
+  la a5,src
+  vld vx1,a5
+  la a6,dest
+  vmsv vx2,a6
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  fence.v.l
+
+  li a2,0
+loop:
+  ld a0,0(a6)
+  ld a1,0(a5)
+  sll a3,a1,32
+  srl a3,a3,32
+  addi x28,a2,2
+  bne a0,a3,fail
+  addi a6,a6,8
+  addi a5,a5,8
+  addi a2,a2,1
+  bne a2,a4,loop
+  j pass
+
+vtcode:
+  utidx x3
+  slli x3,x3,3
+  add x2,x2,x3
+  sw x1,0(x2)
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src:
+#include "data_d.h"
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S
new file mode 100644
index 0000000..95d954c
--- /dev/null
+++ b/isa/rv64uv/utidx.S
@@ -0,0 +1,50 @@
+#*****************************************************************************
+# utidx.S
+#-----------------------------------------------------------------------------
+#
+# Test utidx instruction in a vf block.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a2,2048
+  vvcfgivl a2,a2,2,0
+
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a4,dest
+  vsd vx1,a4
+  fence.v.l
+
+  li a1,1
+loop:
+  ld a0,0(a4)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a4,a4,8
+  addi a1,a1,1
+  bne a1,a2,loop
+  j pass
+
+vtcode:
+  utidx x1
+  addi x1,x1,1
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S
new file mode 100644
index 0000000..869160b
--- /dev/null
+++ b/isa/rv64uv/vfmvv.S
@@ -0,0 +1,52 @@
+#*****************************************************************************
+# vfmvv.S
+#-----------------------------------------------------------------------------
+#
+# Test vfmvv instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a2,2048
+  vvcfgivl a2,a2,2,2
+
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  vfmvv vf1,vf0
+  la a3,dest
+  vfsd vf1,a3
+  fence.v.l
+
+  li a1,1
+loop:
+  ld a0,0(a3)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a3,a3,8
+  addi a1,a1,1
+  bne a1,a2,loop
+  j pass
+
+vtcode:
+  utidx x1
+  addi x1,x1,1
+  mxtf.d f0,x1
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S
new file mode 100644
index 0000000..732f660
--- /dev/null
+++ b/isa/rv64uv/vmsv.S
@@ -0,0 +1,53 @@
+#*****************************************************************************
+# vmsv.S
+#-----------------------------------------------------------------------------
+#
+# Test vmsv instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a2,2048
+  vvcfgivl a2,a2,3,0
+
+  li a3,-1
+  vmsv vx2,a3
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a4,dest
+  vsd vx2,a4
+  fence.v.l
+
+  li a1,0
+loop:
+  ld a0,0(a4)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a4,a4,8
+  addi a1,a1,1
+  bne a1,a2,loop
+  j pass
+
+vtcode:
+  utidx x1
+  addi x1,x1,1
+  add x2,x1,x2
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S
new file mode 100644
index 0000000..17e5865
--- /dev/null
+++ b/isa/rv64uv/vmvv.S
@@ -0,0 +1,51 @@
+#*****************************************************************************
+# vmvv.S
+#-----------------------------------------------------------------------------
+#
+# Test vmvv instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a2,2048
+  vvcfgivl a2,a2,3,0
+
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  vmvv vx2,vx1
+  la a4,dest
+  vsd vx2,a4
+  fence.v.l
+
+  li a1,1
+loop:
+  ld a0,0(a4)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a4,a4,8
+  addi a1,a1,1
+  bne a1,a2,loop
+  j pass
+
+vtcode:
+  utidx x1
+  addi x1,x1,1
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vsetvl.S b/isa/rv64uv/vsetvl.S
new file mode 100644
index 0000000..862e983
--- /dev/null
+++ b/isa/rv64uv/vsetvl.S
@@ -0,0 +1,559 @@
+#*****************************************************************************
+# vsetvl.S
+#-----------------------------------------------------------------------------
+#
+# Test vsetvl instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_VSETVL( 2, 0, 0, 0x07, 768, 768 );
+  TEST_VSETVL( 3, 0, 0, 0x07, 769, 768 );
+  TEST_VSETVL( 4, 0, 0, 0x07, 767, 767 );
+
+  TEST_VSETVL( 5, 0, 0, 0xff, 2048, 2048 );
+  TEST_VSETVL( 6, 0, 0, 0xff, 2049, 2048 );
+  TEST_VSETVL( 7, 0, 0, 0xff, 2047, 2047 );
+
+  TEST_VSETVL( 8, 1, 0, 0x07, 768, 768 );
+  TEST_VSETVL( 9, 1, 0, 0x07, 769, 768 );
+  TEST_VSETVL( 10, 1, 0, 0x07, 767, 767 );
+
+  TEST_VSETVL( 11, 1, 0, 0xff, 2048, 2048 );
+  TEST_VSETVL( 12, 1, 0, 0xff, 2049, 2048 );
+  TEST_VSETVL( 13, 1, 0, 0xff, 2047, 2047 );
+
+  TEST_VSETVL( 14, 2, 0, 0x07, 768, 768 );
+  TEST_VSETVL( 15, 2, 0, 0x07, 769, 768 );
+  TEST_VSETVL( 16, 2, 0, 0x07, 767, 767 );
+
+  TEST_VSETVL( 17, 2, 0, 0xff, 2048, 2048 );
+  TEST_VSETVL( 18, 2, 0, 0xff, 2049, 2048 );
+  TEST_VSETVL( 19, 2, 0, 0xff, 2047, 2047 );
+
+  TEST_VSETVL( 20, 3, 0, 0x07, 384, 384 );
+  TEST_VSETVL( 21, 3, 0, 0x07, 385, 384 );
+  TEST_VSETVL( 22, 3, 0, 0x07, 383, 383 );
+
+  TEST_VSETVL( 23, 3, 0, 0xff, 1024, 1024 );
+  TEST_VSETVL( 24, 3, 0, 0xff, 1025, 1024 );
+  TEST_VSETVL( 25, 3, 0, 0xff, 1023, 1023 );
+
+  TEST_VSETVL( 26, 4, 0, 0x07, 255, 255 );
+  TEST_VSETVL( 27, 4, 0, 0x07, 256, 255 );
+  TEST_VSETVL( 28, 4, 0, 0x07, 254, 254 );
+
+  TEST_VSETVL( 29, 4, 0, 0xff, 680, 680 );
+  TEST_VSETVL( 30, 4, 0, 0xff, 681, 680 );
+  TEST_VSETVL( 31, 4, 0, 0xff, 679, 679 );
+
+  TEST_VSETVL( 32, 5, 0, 0x07, 192, 192 );
+  TEST_VSETVL( 33, 5, 0, 0x07, 193, 192 );
+  TEST_VSETVL( 34, 5, 0, 0x07, 191, 191 );
+
+  TEST_VSETVL( 35, 5, 0, 0xff, 512, 512 );
+  TEST_VSETVL( 36, 5, 0, 0xff, 513, 512 );
+  TEST_VSETVL( 37, 5, 0, 0xff, 511, 511 );
+
+  TEST_VSETVL( 38, 6, 0, 0x07, 153, 153 );
+  TEST_VSETVL( 39, 6, 0, 0x07, 154, 153 );
+  TEST_VSETVL( 40, 6, 0, 0x07, 152, 152 );
+
+  TEST_VSETVL( 41, 6, 0, 0xff, 408, 408 );
+  TEST_VSETVL( 42, 6, 0, 0xff, 409, 408 );
+  TEST_VSETVL( 43, 6, 0, 0xff, 407, 407 );
+
+  TEST_VSETVL( 44, 7, 0, 0x07, 126, 126 );
+  TEST_VSETVL( 45, 7, 0, 0x07, 127, 126 );
+  TEST_VSETVL( 46, 7, 0, 0x07, 125, 125 );
+
+  TEST_VSETVL( 47, 7, 0, 0xff, 336, 336 );
+  TEST_VSETVL( 48, 7, 0, 0xff, 337, 336 );
+  TEST_VSETVL( 49, 7, 0, 0xff, 335, 335 );
+
+  TEST_VSETVL( 50, 8, 0, 0x07, 108, 108 );
+  TEST_VSETVL( 51, 8, 0, 0x07, 109, 108 );
+  TEST_VSETVL( 52, 8, 0, 0x07, 107, 107 );
+
+  TEST_VSETVL( 53, 8, 0, 0xff, 288, 288 );
+  TEST_VSETVL( 54, 8, 0, 0xff, 289, 288 );
+  TEST_VSETVL( 55, 8, 0, 0xff, 287, 287 );
+
+  TEST_VSETVL( 56, 9, 0, 0x07, 96, 96 );
+  TEST_VSETVL( 57, 9, 0, 0x07, 97, 96 );
+  TEST_VSETVL( 58, 9, 0, 0x07, 95, 95 );
+
+  TEST_VSETVL( 59, 9, 0, 0xff, 256, 256 );
+  TEST_VSETVL( 60, 9, 0, 0xff, 257, 256 );
+  TEST_VSETVL( 61, 9, 0, 0xff, 255, 255 );
+
+  TEST_VSETVL( 62, 10, 0, 0x07, 84, 84 );
+  TEST_VSETVL( 63, 10, 0, 0x07, 85, 84 );
+  TEST_VSETVL( 64, 10, 0, 0x07, 83, 83 );
+
+  TEST_VSETVL( 65, 10, 0, 0xff, 224, 224 );
+  TEST_VSETVL( 66, 10, 0, 0xff, 225, 224 );
+  TEST_VSETVL( 67, 10, 0, 0xff, 223, 223 );
+
+  TEST_VSETVL( 68, 11, 0, 0x07, 75, 75 );
+  TEST_VSETVL( 69, 11, 0, 0x07, 76, 75 );
+  TEST_VSETVL( 70, 11, 0, 0x07, 74, 74 );
+
+  TEST_VSETVL( 71, 11, 0, 0xff, 200, 200 );
+  TEST_VSETVL( 72, 11, 0, 0xff, 201, 200 );
+  TEST_VSETVL( 73, 11, 0, 0xff, 199, 199 );
+
+  TEST_VSETVL( 74, 12, 0, 0x07, 69, 69 );
+  TEST_VSETVL( 75, 12, 0, 0x07, 70, 69 );
+  TEST_VSETVL( 76, 12, 0, 0x07, 68, 68 );
+
+  TEST_VSETVL( 77, 12, 0, 0xff, 184, 184 );
+  TEST_VSETVL( 78, 12, 0, 0xff, 185, 184 );
+  TEST_VSETVL( 79, 12, 0, 0xff, 183, 183 );
+
+  TEST_VSETVL( 80, 13, 0, 0x07, 63, 63 );
+  TEST_VSETVL( 81, 13, 0, 0x07, 64, 63 );
+  TEST_VSETVL( 82, 13, 0, 0x07, 62, 62 );
+
+  TEST_VSETVL( 83, 13, 0, 0xff, 168, 168 );
+  TEST_VSETVL( 84, 13, 0, 0xff, 169, 168 );
+  TEST_VSETVL( 85, 13, 0, 0xff, 167, 167 );
+
+  TEST_VSETVL( 86, 14, 0, 0x07, 57, 57 );
+  TEST_VSETVL( 87, 14, 0, 0x07, 58, 57 );
+  TEST_VSETVL( 88, 14, 0, 0x07, 56, 56 );
+
+  TEST_VSETVL( 89, 14, 0, 0xff, 152, 152 );
+  TEST_VSETVL( 90, 14, 0, 0xff, 153, 152 );
+  TEST_VSETVL( 91, 14, 0, 0xff, 151, 151 );
+
+  TEST_VSETVL( 92, 15, 0, 0x07, 54, 54 );
+  TEST_VSETVL( 93, 15, 0, 0x07, 55, 54 );
+  TEST_VSETVL( 94, 15, 0, 0x07, 53, 53 );
+
+  TEST_VSETVL( 95, 15, 0, 0xff, 144, 144 );
+  TEST_VSETVL( 96, 15, 0, 0xff, 145, 144 );
+  TEST_VSETVL( 97, 15, 0, 0xff, 143, 143 );
+
+  TEST_VSETVL( 98, 16, 0, 0x07, 51, 51 );
+  TEST_VSETVL( 99, 16, 0, 0x07, 52, 51 );
+  TEST_VSETVL( 100, 16, 0, 0x07, 50, 50 );
+
+  TEST_VSETVL( 101, 16, 0, 0xff, 136, 136 );
+  TEST_VSETVL( 102, 16, 0, 0xff, 137, 136 );
+  TEST_VSETVL( 103, 16, 0, 0xff, 135, 135 );
+
+  TEST_VSETVL( 104, 17, 0, 0x07, 48, 48 );
+  TEST_VSETVL( 105, 17, 0, 0x07, 49, 48 );
+  TEST_VSETVL( 106, 17, 0, 0x07, 47, 47 );
+
+  TEST_VSETVL( 107, 17, 0, 0xff, 128, 128 );
+  TEST_VSETVL( 108, 17, 0, 0xff, 129, 128 );
+  TEST_VSETVL( 109, 17, 0, 0xff, 127, 127 );
+
+  TEST_VSETVL( 110, 18, 0, 0x07, 45, 45 );
+  TEST_VSETVL( 111, 18, 0, 0x07, 46, 45 );
+  TEST_VSETVL( 112, 18, 0, 0x07, 44, 44 );
+
+  TEST_VSETVL( 113, 18, 0, 0xff, 120, 120 );
+  TEST_VSETVL( 114, 18, 0, 0xff, 121, 120 );
+  TEST_VSETVL( 115, 18, 0, 0xff, 119, 119 );
+
+  TEST_VSETVL( 116, 19, 0, 0x07, 42, 42 );
+  TEST_VSETVL( 117, 19, 0, 0x07, 43, 42 );
+  TEST_VSETVL( 118, 19, 0, 0x07, 41, 41 );
+
+  TEST_VSETVL( 119, 19, 0, 0xff, 112, 112 );
+  TEST_VSETVL( 120, 19, 0, 0xff, 113, 112 );
+  TEST_VSETVL( 121, 19, 0, 0xff, 111, 111 );
+
+  TEST_VSETVL( 122, 20, 0, 0x07, 39, 39 );
+  TEST_VSETVL( 123, 20, 0, 0x07, 40, 39 );
+  TEST_VSETVL( 124, 20, 0, 0x07, 38, 38 );
+
+  TEST_VSETVL( 125, 20, 0, 0xff, 104, 104 );
+  TEST_VSETVL( 126, 20, 0, 0xff, 105, 104 );
+  TEST_VSETVL( 127, 20, 0, 0xff, 103, 103 );
+
+  TEST_VSETVL( 128, 21, 0, 0x07, 36, 36 );
+  TEST_VSETVL( 129, 21, 0, 0x07, 37, 36 );
+  TEST_VSETVL( 130, 21, 0, 0x07, 35, 35 );
+
+  TEST_VSETVL( 131, 21, 0, 0xff, 96, 96 );
+  TEST_VSETVL( 132, 21, 0, 0xff, 97, 96 );
+  TEST_VSETVL( 133, 21, 0, 0xff, 95, 95 );
+
+  TEST_VSETVL( 134, 22, 0, 0x07, 36, 36 );
+  TEST_VSETVL( 135, 22, 0, 0x07, 37, 36 );
+  TEST_VSETVL( 136, 22, 0, 0x07, 35, 35 );
+
+  TEST_VSETVL( 137, 22, 0, 0xff, 96, 96 );
+  TEST_VSETVL( 138, 22, 0, 0xff, 97, 96 );
+  TEST_VSETVL( 139, 22, 0, 0xff, 95, 95 );
+
+  TEST_VSETVL( 140, 23, 0, 0x07, 33, 33 );
+  TEST_VSETVL( 141, 23, 0, 0x07, 34, 33 );
+  TEST_VSETVL( 142, 23, 0, 0x07, 32, 32 );
+
+  TEST_VSETVL( 143, 23, 0, 0xff, 88, 88 );
+  TEST_VSETVL( 144, 23, 0, 0xff, 89, 88 );
+  TEST_VSETVL( 145, 23, 0, 0xff, 87, 87 );
+
+  TEST_VSETVL( 146, 24, 0, 0x07, 33, 33 );
+  TEST_VSETVL( 147, 24, 0, 0x07, 34, 33 );
+  TEST_VSETVL( 148, 24, 0, 0x07, 32, 32 );
+
+  TEST_VSETVL( 149, 24, 0, 0xff, 88, 88 );
+  TEST_VSETVL( 150, 24, 0, 0xff, 89, 88 );
+  TEST_VSETVL( 151, 24, 0, 0xff, 87, 87 );
+
+  TEST_VSETVL( 152, 25, 0, 0x07, 30, 30 );
+  TEST_VSETVL( 153, 25, 0, 0x07, 31, 30 );
+  TEST_VSETVL( 154, 25, 0, 0x07, 29, 29 );
+
+  TEST_VSETVL( 155, 25, 0, 0xff, 80, 80 );
+  TEST_VSETVL( 156, 25, 0, 0xff, 81, 80 );
+  TEST_VSETVL( 157, 25, 0, 0xff, 79, 79 );
+
+  TEST_VSETVL( 158, 26, 0, 0x07, 30, 30 );
+  TEST_VSETVL( 159, 26, 0, 0x07, 31, 30 );
+  TEST_VSETVL( 160, 26, 0, 0x07, 29, 29 );
+
+  TEST_VSETVL( 161, 26, 0, 0xff, 80, 80 );
+  TEST_VSETVL( 162, 26, 0, 0xff, 81, 80 );
+  TEST_VSETVL( 163, 26, 0, 0xff, 79, 79 );
+
+  TEST_VSETVL( 164, 27, 0, 0x07, 27, 27 );
+  TEST_VSETVL( 165, 27, 0, 0x07, 28, 27 );
+  TEST_VSETVL( 166, 27, 0, 0x07, 26, 26 );
+
+  TEST_VSETVL( 167, 27, 0, 0xff, 72, 72 );
+  TEST_VSETVL( 168, 27, 0, 0xff, 73, 72 );
+  TEST_VSETVL( 169, 27, 0, 0xff, 71, 71 );
+
+  TEST_VSETVL( 170, 28, 0, 0x07, 27, 27 );
+  TEST_VSETVL( 171, 28, 0, 0x07, 28, 27 );
+  TEST_VSETVL( 172, 28, 0, 0x07, 26, 26 );
+
+  TEST_VSETVL( 173, 28, 0, 0xff, 72, 72 );
+  TEST_VSETVL( 174, 28, 0, 0xff, 73, 72 );
+  TEST_VSETVL( 175, 28, 0, 0xff, 71, 71 );
+
+  TEST_VSETVL( 176, 29, 0, 0x07, 27, 27 );
+  TEST_VSETVL( 177, 29, 0, 0x07, 28, 27 );
+  TEST_VSETVL( 178, 29, 0, 0x07, 26, 26 );
+
+  TEST_VSETVL( 179, 29, 0, 0xff, 72, 72 );
+  TEST_VSETVL( 180, 29, 0, 0xff, 73, 72 );
+  TEST_VSETVL( 181, 29, 0, 0xff, 71, 71 );
+
+  TEST_VSETVL( 182, 30, 0, 0x07, 24, 24 );
+  TEST_VSETVL( 183, 30, 0, 0x07, 25, 24 );
+  TEST_VSETVL( 184, 30, 0, 0x07, 23, 23 );
+
+  TEST_VSETVL( 185, 30, 0, 0xff, 64, 64 );
+  TEST_VSETVL( 186, 30, 0, 0xff, 65, 64 );
+  TEST_VSETVL( 187, 30, 0, 0xff, 63, 63 );
+
+  TEST_VSETVL( 188, 31, 0, 0x07, 24, 24 );
+  TEST_VSETVL( 189, 31, 0, 0x07, 25, 24 );
+  TEST_VSETVL( 190, 31, 0, 0x07, 23, 23 );
+
+  TEST_VSETVL( 191, 31, 0, 0xff, 64, 64 );
+  TEST_VSETVL( 192, 31, 0, 0xff, 65, 64 );
+  TEST_VSETVL( 193, 31, 0, 0xff, 63, 63 );
+
+  TEST_VSETVL( 194, 32, 0, 0x07, 24, 24 );
+  TEST_VSETVL( 195, 32, 0, 0x07, 25, 24 );
+  TEST_VSETVL( 196, 32, 0, 0x07, 23, 23 );
+
+  TEST_VSETVL( 197, 32, 0, 0xff, 64, 64 );
+  TEST_VSETVL( 198, 32, 0, 0xff, 65, 64 );
+  TEST_VSETVL( 199, 32, 0, 0xff, 63, 63 );
+
+  TEST_VSETVL( 200, 32, 0, 0x07, 24, 24 );
+  TEST_VSETVL( 201, 32, 0, 0x07, 25, 24 );
+  TEST_VSETVL( 202, 32, 0, 0x07, 23, 23 );
+
+  TEST_VSETVL( 203, 32, 0, 0xff, 64, 64 );
+  TEST_VSETVL( 204, 32, 0, 0xff, 65, 64 );
+  TEST_VSETVL( 205, 32, 0, 0xff, 63, 63 );
+
+  TEST_VSETVL( 206, 32, 1, 0x07, 24, 24 );
+  TEST_VSETVL( 207, 32, 1, 0x07, 25, 24 );
+  TEST_VSETVL( 208, 32, 1, 0x07, 23, 23 );
+
+  TEST_VSETVL( 209, 32, 1, 0xff, 64, 64 );
+  TEST_VSETVL( 210, 32, 1, 0xff, 65, 64 );
+  TEST_VSETVL( 211, 32, 1, 0xff, 63, 63 );
+
+  TEST_VSETVL( 212, 32, 2, 0x07, 21, 21 );
+  TEST_VSETVL( 213, 32, 2, 0x07, 22, 21 );
+  TEST_VSETVL( 214, 32, 2, 0x07, 20, 20 );
+
+  TEST_VSETVL( 215, 32, 2, 0xff, 56, 56 );
+  TEST_VSETVL( 216, 32, 2, 0xff, 57, 56 );
+  TEST_VSETVL( 217, 32, 2, 0xff, 55, 55 );
+
+  TEST_VSETVL( 218, 32, 3, 0x07, 21, 21 );
+  TEST_VSETVL( 219, 32, 3, 0x07, 22, 21 );
+  TEST_VSETVL( 220, 32, 3, 0x07, 20, 20 );
+
+  TEST_VSETVL( 221, 32, 3, 0xff, 56, 56 );
+  TEST_VSETVL( 222, 32, 3, 0xff, 57, 56 );
+  TEST_VSETVL( 223, 32, 3, 0xff, 55, 55 );
+
+  TEST_VSETVL( 224, 32, 4, 0x07, 21, 21 );
+  TEST_VSETVL( 225, 32, 4, 0x07, 22, 21 );
+  TEST_VSETVL( 226, 32, 4, 0x07, 20, 20 );
+
+  TEST_VSETVL( 227, 32, 4, 0xff, 56, 56 );
+  TEST_VSETVL( 228, 32, 4, 0xff, 57, 56 );
+  TEST_VSETVL( 229, 32, 4, 0xff, 55, 55 );
+
+  TEST_VSETVL( 230, 32, 5, 0x07, 21, 21 );
+  TEST_VSETVL( 231, 32, 5, 0x07, 22, 21 );
+  TEST_VSETVL( 232, 32, 5, 0x07, 20, 20 );
+
+  TEST_VSETVL( 233, 32, 5, 0xff, 56, 56 );
+  TEST_VSETVL( 234, 32, 5, 0xff, 57, 56 );
+  TEST_VSETVL( 235, 32, 5, 0xff, 55, 55 );
+
+  TEST_VSETVL( 236, 32, 6, 0x07, 18, 18 );
+  TEST_VSETVL( 237, 32, 6, 0x07, 19, 18 );
+  TEST_VSETVL( 238, 32, 6, 0x07, 17, 17 );
+
+  TEST_VSETVL( 239, 32, 6, 0xff, 48, 48 );
+  TEST_VSETVL( 240, 32, 6, 0xff, 49, 48 );
+  TEST_VSETVL( 241, 32, 6, 0xff, 47, 47 );
+
+  TEST_VSETVL( 242, 32, 7, 0x07, 18, 18 );
+  TEST_VSETVL( 243, 32, 7, 0x07, 19, 18 );
+  TEST_VSETVL( 244, 32, 7, 0x07, 17, 17 );
+
+  TEST_VSETVL( 245, 32, 7, 0xff, 48, 48 );
+  TEST_VSETVL( 246, 32, 7, 0xff, 49, 48 );
+  TEST_VSETVL( 247, 32, 7, 0xff, 47, 47 );
+
+  TEST_VSETVL( 248, 32, 8, 0x07, 18, 18 );
+  TEST_VSETVL( 249, 32, 8, 0x07, 19, 18 );
+  TEST_VSETVL( 250, 32, 8, 0x07, 17, 17 );
+
+  TEST_VSETVL( 251, 32, 8, 0xff, 48, 48 );
+  TEST_VSETVL( 252, 32, 8, 0xff, 49, 48 );
+  TEST_VSETVL( 253, 32, 8, 0xff, 47, 47 );
+
+  TEST_VSETVL( 254, 32, 9, 0x07, 18, 18 );
+  TEST_VSETVL( 255, 32, 9, 0x07, 19, 18 );
+  TEST_VSETVL( 256, 32, 9, 0x07, 17, 17 );
+
+  TEST_VSETVL( 257, 32, 9, 0xff, 48, 48 );
+  TEST_VSETVL( 258, 32, 9, 0xff, 49, 48 );
+  TEST_VSETVL( 259, 32, 9, 0xff, 47, 47 );
+
+  TEST_VSETVL( 260, 32, 10, 0x07, 18, 18 );
+  TEST_VSETVL( 261, 32, 10, 0x07, 19, 18 );
+  TEST_VSETVL( 262, 32, 10, 0x07, 17, 17 );
+
+  TEST_VSETVL( 263, 32, 10, 0xff, 48, 48 );
+  TEST_VSETVL( 264, 32, 10, 0xff, 49, 48 );
+  TEST_VSETVL( 265, 32, 10, 0xff, 47, 47 );
+
+  TEST_VSETVL( 266, 32, 11, 0x07, 18, 18 );
+  TEST_VSETVL( 267, 32, 11, 0x07, 19, 18 );
+  TEST_VSETVL( 268, 32, 11, 0x07, 17, 17 );
+
+  TEST_VSETVL( 269, 32, 11, 0xff, 48, 48 );
+  TEST_VSETVL( 270, 32, 11, 0xff, 49, 48 );
+  TEST_VSETVL( 271, 32, 11, 0xff, 47, 47 );
+
+  TEST_VSETVL( 272, 32, 12, 0x07, 15, 15 );
+  TEST_VSETVL( 273, 32, 12, 0x07, 16, 15 );
+  TEST_VSETVL( 274, 32, 12, 0x07, 14, 14 );
+
+  TEST_VSETVL( 275, 32, 12, 0xff, 40, 40 );
+  TEST_VSETVL( 276, 32, 12, 0xff, 41, 40 );
+  TEST_VSETVL( 277, 32, 12, 0xff, 39, 39 );
+
+  TEST_VSETVL( 278, 32, 13, 0x07, 15, 15 );
+  TEST_VSETVL( 279, 32, 13, 0x07, 16, 15 );
+  TEST_VSETVL( 280, 32, 13, 0x07, 14, 14 );
+
+  TEST_VSETVL( 281, 32, 13, 0xff, 40, 40 );
+  TEST_VSETVL( 282, 32, 13, 0xff, 41, 40 );
+  TEST_VSETVL( 283, 32, 13, 0xff, 39, 39 );
+
+  TEST_VSETVL( 284, 32, 14, 0x07, 15, 15 );
+  TEST_VSETVL( 285, 32, 14, 0x07, 16, 15 );
+  TEST_VSETVL( 286, 32, 14, 0x07, 14, 14 );
+
+  TEST_VSETVL( 287, 32, 14, 0xff, 40, 40 );
+  TEST_VSETVL( 288, 32, 14, 0xff, 41, 40 );
+  TEST_VSETVL( 289, 32, 14, 0xff, 39, 39 );
+
+  TEST_VSETVL( 290, 32, 15, 0x07, 15, 15 );
+  TEST_VSETVL( 291, 32, 15, 0x07, 16, 15 );
+  TEST_VSETVL( 292, 32, 15, 0x07, 14, 14 );
+
+  TEST_VSETVL( 293, 32, 15, 0xff, 40, 40 );
+  TEST_VSETVL( 294, 32, 15, 0xff, 41, 40 );
+  TEST_VSETVL( 295, 32, 15, 0xff, 39, 39 );
+
+  TEST_VSETVL( 296, 32, 16, 0x07, 15, 15 );
+  TEST_VSETVL( 297, 32, 16, 0x07, 16, 15 );
+  TEST_VSETVL( 298, 32, 16, 0x07, 14, 14 );
+
+  TEST_VSETVL( 299, 32, 16, 0xff, 40, 40 );
+  TEST_VSETVL( 300, 32, 16, 0xff, 41, 40 );
+  TEST_VSETVL( 301, 32, 16, 0xff, 39, 39 );
+
+  TEST_VSETVL( 302, 32, 17, 0x07, 15, 15 );
+  TEST_VSETVL( 303, 32, 17, 0x07, 16, 15 );
+  TEST_VSETVL( 304, 32, 17, 0x07, 14, 14 );
+
+  TEST_VSETVL( 305, 32, 17, 0xff, 40, 40 );
+  TEST_VSETVL( 306, 32, 17, 0xff, 41, 40 );
+  TEST_VSETVL( 307, 32, 17, 0xff, 39, 39 );
+
+  TEST_VSETVL( 308, 32, 18, 0x07, 15, 15 );
+  TEST_VSETVL( 309, 32, 18, 0x07, 16, 15 );
+  TEST_VSETVL( 310, 32, 18, 0x07, 14, 14 );
+
+  TEST_VSETVL( 311, 32, 18, 0xff, 40, 40 );
+  TEST_VSETVL( 312, 32, 18, 0xff, 41, 40 );
+  TEST_VSETVL( 313, 32, 18, 0xff, 39, 39 );
+
+  TEST_VSETVL( 314, 32, 19, 0x07, 15, 15 );
+  TEST_VSETVL( 315, 32, 19, 0x07, 16, 15 );
+  TEST_VSETVL( 316, 32, 19, 0x07, 14, 14 );
+
+  TEST_VSETVL( 317, 32, 19, 0xff, 40, 40 );
+  TEST_VSETVL( 318, 32, 19, 0xff, 41, 40 );
+  TEST_VSETVL( 319, 32, 19, 0xff, 39, 39 );
+
+  TEST_VSETVL( 320, 32, 20, 0x07, 15, 15 );
+  TEST_VSETVL( 321, 32, 20, 0x07, 16, 15 );
+  TEST_VSETVL( 322, 32, 20, 0x07, 14, 14 );
+
+  TEST_VSETVL( 323, 32, 20, 0xff, 40, 40 );
+  TEST_VSETVL( 324, 32, 20, 0xff, 41, 40 );
+  TEST_VSETVL( 325, 32, 20, 0xff, 39, 39 );
+
+  TEST_VSETVL( 326, 32, 21, 0x07, 12, 12 );
+  TEST_VSETVL( 327, 32, 21, 0x07, 13, 12 );
+  TEST_VSETVL( 328, 32, 21, 0x07, 11, 11 );
+
+  TEST_VSETVL( 329, 32, 21, 0xff, 32, 32 );
+  TEST_VSETVL( 330, 32, 21, 0xff, 33, 32 );
+  TEST_VSETVL( 331, 32, 21, 0xff, 31, 31 );
+
+  TEST_VSETVL( 332, 32, 22, 0x07, 12, 12 );
+  TEST_VSETVL( 333, 32, 22, 0x07, 13, 12 );
+  TEST_VSETVL( 334, 32, 22, 0x07, 11, 11 );
+
+  TEST_VSETVL( 335, 32, 22, 0xff, 32, 32 );
+  TEST_VSETVL( 336, 32, 22, 0xff, 33, 32 );
+  TEST_VSETVL( 337, 32, 22, 0xff, 31, 31 );
+
+  TEST_VSETVL( 338, 32, 23, 0x07, 12, 12 );
+  TEST_VSETVL( 339, 32, 23, 0x07, 13, 12 );
+  TEST_VSETVL( 340, 32, 23, 0x07, 11, 11 );
+
+  TEST_VSETVL( 341, 32, 23, 0xff, 32, 32 );
+  TEST_VSETVL( 342, 32, 23, 0xff, 33, 32 );
+  TEST_VSETVL( 343, 32, 23, 0xff, 31, 31 );
+
+  TEST_VSETVL( 344, 32, 24, 0x07, 12, 12 );
+  TEST_VSETVL( 345, 32, 24, 0x07, 13, 12 );
+  TEST_VSETVL( 346, 32, 24, 0x07, 11, 11 );
+
+  TEST_VSETVL( 347, 32, 24, 0xff, 32, 32 );
+  TEST_VSETVL( 348, 32, 24, 0xff, 33, 32 );
+  TEST_VSETVL( 349, 32, 24, 0xff, 31, 31 );
+
+  TEST_VSETVL( 350, 32, 25, 0x07, 12, 12 );
+  TEST_VSETVL( 351, 32, 25, 0x07, 13, 12 );
+  TEST_VSETVL( 352, 32, 25, 0x07, 11, 11 );
+
+  TEST_VSETVL( 353, 32, 25, 0xff, 32, 32 );
+  TEST_VSETVL( 354, 32, 25, 0xff, 33, 32 );
+  TEST_VSETVL( 355, 32, 25, 0xff, 31, 31 );
+
+  TEST_VSETVL( 356, 32, 26, 0x07, 12, 12 );
+  TEST_VSETVL( 357, 32, 26, 0x07, 13, 12 );
+  TEST_VSETVL( 358, 32, 26, 0x07, 11, 11 );
+
+  TEST_VSETVL( 359, 32, 26, 0xff, 32, 32 );
+  TEST_VSETVL( 360, 32, 26, 0xff, 33, 32 );
+  TEST_VSETVL( 361, 32, 26, 0xff, 31, 31 );
+
+  TEST_VSETVL( 362, 32, 27, 0x07, 12, 12 );
+  TEST_VSETVL( 363, 32, 27, 0x07, 13, 12 );
+  TEST_VSETVL( 364, 32, 27, 0x07, 11, 11 );
+
+  TEST_VSETVL( 365, 32, 27, 0xff, 32, 32 );
+  TEST_VSETVL( 366, 32, 27, 0xff, 33, 32 );
+  TEST_VSETVL( 367, 32, 27, 0xff, 31, 31 );
+
+  TEST_VSETVL( 368, 32, 28, 0x07, 12, 12 );
+  TEST_VSETVL( 369, 32, 28, 0x07, 13, 12 );
+  TEST_VSETVL( 370, 32, 28, 0x07, 11, 11 );
+
+  TEST_VSETVL( 371, 32, 28, 0xff, 32, 32 );
+  TEST_VSETVL( 372, 32, 28, 0xff, 33, 32 );
+  TEST_VSETVL( 373, 32, 28, 0xff, 31, 31 );
+
+  TEST_VSETVL( 374, 32, 29, 0x07, 12, 12 );
+  TEST_VSETVL( 375, 32, 29, 0x07, 13, 12 );
+  TEST_VSETVL( 376, 32, 29, 0x07, 11, 11 );
+
+  TEST_VSETVL( 377, 32, 29, 0xff, 32, 32 );
+  TEST_VSETVL( 378, 32, 29, 0xff, 33, 32 );
+  TEST_VSETVL( 379, 32, 29, 0xff, 31, 31 );
+
+  TEST_VSETVL( 380, 32, 30, 0x07, 12, 12 );
+  TEST_VSETVL( 381, 32, 30, 0x07, 13, 12 );
+  TEST_VSETVL( 382, 32, 30, 0x07, 11, 11 );
+
+  TEST_VSETVL( 383, 32, 30, 0xff, 32, 32 );
+  TEST_VSETVL( 384, 32, 30, 0xff, 33, 32 );
+  TEST_VSETVL( 385, 32, 30, 0xff, 31, 31 );
+
+  TEST_VSETVL( 386, 32, 31, 0x07, 12, 12 );
+  TEST_VSETVL( 387, 32, 31, 0x07, 13, 12 );
+  TEST_VSETVL( 388, 32, 31, 0x07, 11, 11 );
+
+  TEST_VSETVL( 389, 32, 31, 0xff, 32, 32 );
+  TEST_VSETVL( 390, 32, 31, 0xff, 33, 32 );
+  TEST_VSETVL( 391, 32, 31, 0xff, 31, 31 );
+
+  TEST_VSETVL( 392, 32, 32, 0x07, 12, 12 );
+  TEST_VSETVL( 393, 32, 32, 0x07, 13, 12 );
+  TEST_VSETVL( 394, 32, 32, 0x07, 11, 11 );
+
+  TEST_VSETVL( 395, 32, 32, 0xff, 32, 32 );
+  TEST_VSETVL( 396, 32, 32, 0xff, 33, 32 );
+  TEST_VSETVL( 397, 32, 32, 0xff, 31, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S
new file mode 100644
index 0000000..191408d
--- /dev/null
+++ b/isa/rv64uv/vvadd_branch.S
@@ -0,0 +1,141 @@
+#*****************************************************************************
+# vvadd_branch.S
+#-----------------------------------------------------------------------------
+#
+# Test vvadd branch.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,8
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li a2, 6        
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li a2, 4        
+  li x28,4
+  bne a1,a2,fail
+  li a2, 2
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  la a3,src1
+  vld vx4,a3
+  li a4, 3
+  vmsv vx5,a4
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx4,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,1
+  li x28,6
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li a2,2
+  li x28,7
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li a2,0
+  li x28,8
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li a2,0
+  li x28,9
+  bne a1,a2,fail
+
+  la a3,src2
+  vld vx5,a3
+  lui a0,%hi(vtcode3)
+  vf %lo(vtcode3)(a0)
+  la a5,dest
+  vsd vx5,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,4
+  li x28,6
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li a2,3
+  li x28,7
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li a2,2
+  li x28,8
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li a2,1
+  li x28,9
+  bne a1,a2,fail
+
+  j pass
+
+vtcode1:
+  beq x2, x2, end
+  add x2,x2,x3
+end:    add x2, x3, x3
+  stop
+
+vtcode2:
+  blt x4, x5, end2
+  add x4, x0, x0
+end2:   add x4, x4, x0
+  stop
+
+vtcode3:
+  bge x5, x0, end3
+  add x5, x0, x0
+end3:   add x5, x5,x0
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvadd_d.S b/isa/rv64uv/vvadd_d.S
new file mode 100644
index 0000000..ae9db03
--- /dev/null
+++ b/isa/rv64uv/vvadd_d.S
@@ -0,0 +1,130 @@
+#*****************************************************************************
+# vvadd_d.S
+#-----------------------------------------------------------------------------
+#
+# Test vvadd d.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  la a3,src1
+  vld vx4,a3
+  lui a0,%hi(vtcode2)
+  vf %lo(vtcode2)(a0)
+  la a5,dest
+  vsd vx4,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,1
+  li x28,6
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li a2,2
+  li x28,7
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li a2,3
+  li x28,8
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li a2,4
+  li x28,9
+  bne a1,a2,fail
+
+  la a3,src2
+  vld vx5,a3
+  lui a0,%hi(vtcode3)
+  vf %lo(vtcode3)(a0)
+  la a5,dest
+  vsd vx5,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,4
+  li x28,6
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li a2,3
+  li x28,7
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li a2,2
+  li x28,8
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li a2,1
+  li x28,9
+  bne a1,a2,fail
+
+  j pass
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+vtcode2:
+  add a0,a0,x0
+  stop
+
+vtcode3:
+  add a1,a1,x0
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
new file mode 100644
index 0000000..bcd417a
--- /dev/null
+++ b/isa/rv64uv/vvadd_fd.S
@@ -0,0 +1,76 @@
+#*****************************************************************************
+# vvadd_fd.S
+#-----------------------------------------------------------------------------
+#
+# Test vvadd fd.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,4
+  vvcfgivl a3,a3,32,32
+
+  la a3,src1
+  la a4,src2
+  vfld vf2,a3
+  vfld vf3,a4
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a5,dest
+  vfsd vf2,a5
+  fence.v.l
+  la a5,result
+  ld a1,0(a5)
+  ld a2,0(a5)
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+  j pass
+
+vtcode:
+  fadd.d f2,f2,f3
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .double 0.1
+  .double 0.2
+  .double 0.3
+  .double 0.4
+src2:
+  .double 0.4
+  .double 0.3
+  .double 0.2
+  .double 0.1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+result:
+  .double 0.5
+  .double 0.5
+  .double 0.5
+  .double 0.5
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvadd_fw.S b/isa/rv64uv/vvadd_fw.S
new file mode 100644
index 0000000..f857237
--- /dev/null
+++ b/isa/rv64uv/vvadd_fw.S
@@ -0,0 +1,76 @@
+#*****************************************************************************
+# vvadd_fw.S
+#-----------------------------------------------------------------------------
+#
+# Test vvadd fw.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,4
+  vvcfgivl a3,a3,32,32
+
+  la a3,src1
+  la a4,src2
+  vflw vf2,a3
+  vflw vf3,a4
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a5,dest
+  vfsw vf2,a5
+  fence.v.l
+  la a6,result
+  lw a1,0(a5)
+  lw a2,0(a6)
+  li x28,2
+  bne a1,a2,fail
+  lw a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  lw a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  lw a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+  j pass
+
+vtcode:
+  fadd.s f2,f2,f3
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .single 0.1
+  .single 0.2
+  .single 0.3
+  .single 0.4
+src2:
+  .single 0.4
+  .single 0.3
+  .single 0.2
+  .single 0.1
+dest:
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+result:
+  .single 0.5
+  .single 0.5
+  .single 0.5
+  .single 0.5
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
new file mode 100644
index 0000000..f4ad1ca
--- /dev/null
+++ b/isa/rv64uv/vvadd_w.S
@@ -0,0 +1,85 @@
+#*****************************************************************************
+# vvadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test vvadd w.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,9
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vlw vx2,a3
+  vlw vx3,a4
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a5,dest
+  vsw vx2,a5
+  fence.v.l
+  lw a1,0(a5)
+  li a2,10
+  li x28,2
+  bne a1,a2,fail
+  lw a1,4(a5)
+  li x28,3
+  bne a1,a2,fail
+  lw a1,8(a5)
+  li x28,4
+  bne a1,a2,fail
+  lw a1,12(a5)
+  li x28,5
+  bne a1,a2,fail
+  j pass
+
+vtcode:
+  addw x2,x2,x3
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .word 1
+  .word 2
+  .word 3
+  .word 4
+  .word 5
+  .word 6
+  .word 7
+  .word 8
+  .word 9
+src2:
+  .word 9
+  .word 8
+  .word 7
+  .word 6
+  .word 5
+  .word 4
+  .word 3
+  .word 2
+  .word 1
+dest:
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+  .word 0xdeadbeef
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvcfg.S b/isa/rv64uv/vvcfg.S
new file mode 100644
index 0000000..e474d60
--- /dev/null
+++ b/isa/rv64uv/vvcfg.S
@@ -0,0 +1,559 @@
+#*****************************************************************************
+# vvcfg.S
+#-----------------------------------------------------------------------------
+#
+# Test vvcfg instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_VVCFG( 2, 0, 0, 0x07, 768, 768 );
+  TEST_VVCFG( 3, 0, 0, 0x07, 769, 768 );
+  TEST_VVCFG( 4, 0, 0, 0x07, 767, 767 );
+
+  TEST_VVCFG( 5, 0, 0, 0xff, 2048, 2048 );
+  TEST_VVCFG( 6, 0, 0, 0xff, 2049, 2048 );
+  TEST_VVCFG( 7, 0, 0, 0xff, 2047, 2047 );
+
+  TEST_VVCFG( 8, 1, 0, 0x07, 768, 768 );
+  TEST_VVCFG( 9, 1, 0, 0x07, 769, 768 );
+  TEST_VVCFG( 10, 1, 0, 0x07, 767, 767 );
+
+  TEST_VVCFG( 11, 1, 0, 0xff, 2048, 2048 );
+  TEST_VVCFG( 12, 1, 0, 0xff, 2049, 2048 );
+  TEST_VVCFG( 13, 1, 0, 0xff, 2047, 2047 );
+
+  TEST_VVCFG( 14, 2, 0, 0x07, 768, 768 );
+  TEST_VVCFG( 15, 2, 0, 0x07, 769, 768 );
+  TEST_VVCFG( 16, 2, 0, 0x07, 767, 767 );
+
+  TEST_VVCFG( 17, 2, 0, 0xff, 2048, 2048 );
+  TEST_VVCFG( 18, 2, 0, 0xff, 2049, 2048 );
+  TEST_VVCFG( 19, 2, 0, 0xff, 2047, 2047 );
+
+  TEST_VVCFG( 20, 3, 0, 0x07, 384, 384 );
+  TEST_VVCFG( 21, 3, 0, 0x07, 385, 384 );
+  TEST_VVCFG( 22, 3, 0, 0x07, 383, 383 );
+
+  TEST_VVCFG( 23, 3, 0, 0xff, 1024, 1024 );
+  TEST_VVCFG( 24, 3, 0, 0xff, 1025, 1024 );
+  TEST_VVCFG( 25, 3, 0, 0xff, 1023, 1023 );
+
+  TEST_VVCFG( 26, 4, 0, 0x07, 255, 255 );
+  TEST_VVCFG( 27, 4, 0, 0x07, 256, 255 );
+  TEST_VVCFG( 28, 4, 0, 0x07, 254, 254 );
+
+  TEST_VVCFG( 29, 4, 0, 0xff, 680, 680 );
+  TEST_VVCFG( 30, 4, 0, 0xff, 681, 680 );
+  TEST_VVCFG( 31, 4, 0, 0xff, 679, 679 );
+
+  TEST_VVCFG( 32, 5, 0, 0x07, 192, 192 );
+  TEST_VVCFG( 33, 5, 0, 0x07, 193, 192 );
+  TEST_VVCFG( 34, 5, 0, 0x07, 191, 191 );
+
+  TEST_VVCFG( 35, 5, 0, 0xff, 512, 512 );
+  TEST_VVCFG( 36, 5, 0, 0xff, 513, 512 );
+  TEST_VVCFG( 37, 5, 0, 0xff, 511, 511 );
+
+  TEST_VVCFG( 38, 6, 0, 0x07, 153, 153 );
+  TEST_VVCFG( 39, 6, 0, 0x07, 154, 153 );
+  TEST_VVCFG( 40, 6, 0, 0x07, 152, 152 );
+
+  TEST_VVCFG( 41, 6, 0, 0xff, 408, 408 );
+  TEST_VVCFG( 42, 6, 0, 0xff, 409, 408 );
+  TEST_VVCFG( 43, 6, 0, 0xff, 407, 407 );
+
+  TEST_VVCFG( 44, 7, 0, 0x07, 126, 126 );
+  TEST_VVCFG( 45, 7, 0, 0x07, 127, 126 );
+  TEST_VVCFG( 46, 7, 0, 0x07, 125, 125 );
+
+  TEST_VVCFG( 47, 7, 0, 0xff, 336, 336 );
+  TEST_VVCFG( 48, 7, 0, 0xff, 337, 336 );
+  TEST_VVCFG( 49, 7, 0, 0xff, 335, 335 );
+
+  TEST_VVCFG( 50, 8, 0, 0x07, 108, 108 );
+  TEST_VVCFG( 51, 8, 0, 0x07, 109, 108 );
+  TEST_VVCFG( 52, 8, 0, 0x07, 107, 107 );
+
+  TEST_VVCFG( 53, 8, 0, 0xff, 288, 288 );
+  TEST_VVCFG( 54, 8, 0, 0xff, 289, 288 );
+  TEST_VVCFG( 55, 8, 0, 0xff, 287, 287 );
+
+  TEST_VVCFG( 56, 9, 0, 0x07, 96, 96 );
+  TEST_VVCFG( 57, 9, 0, 0x07, 97, 96 );
+  TEST_VVCFG( 58, 9, 0, 0x07, 95, 95 );
+
+  TEST_VVCFG( 59, 9, 0, 0xff, 256, 256 );
+  TEST_VVCFG( 60, 9, 0, 0xff, 257, 256 );
+  TEST_VVCFG( 61, 9, 0, 0xff, 255, 255 );
+
+  TEST_VVCFG( 62, 10, 0, 0x07, 84, 84 );
+  TEST_VVCFG( 63, 10, 0, 0x07, 85, 84 );
+  TEST_VVCFG( 64, 10, 0, 0x07, 83, 83 );
+
+  TEST_VVCFG( 65, 10, 0, 0xff, 224, 224 );
+  TEST_VVCFG( 66, 10, 0, 0xff, 225, 224 );
+  TEST_VVCFG( 67, 10, 0, 0xff, 223, 223 );
+
+  TEST_VVCFG( 68, 11, 0, 0x07, 75, 75 );
+  TEST_VVCFG( 69, 11, 0, 0x07, 76, 75 );
+  TEST_VVCFG( 70, 11, 0, 0x07, 74, 74 );
+
+  TEST_VVCFG( 71, 11, 0, 0xff, 200, 200 );
+  TEST_VVCFG( 72, 11, 0, 0xff, 201, 200 );
+  TEST_VVCFG( 73, 11, 0, 0xff, 199, 199 );
+
+  TEST_VVCFG( 74, 12, 0, 0x07, 69, 69 );
+  TEST_VVCFG( 75, 12, 0, 0x07, 70, 69 );
+  TEST_VVCFG( 76, 12, 0, 0x07, 68, 68 );
+
+  TEST_VVCFG( 77, 12, 0, 0xff, 184, 184 );
+  TEST_VVCFG( 78, 12, 0, 0xff, 185, 184 );
+  TEST_VVCFG( 79, 12, 0, 0xff, 183, 183 );
+
+  TEST_VVCFG( 80, 13, 0, 0x07, 63, 63 );
+  TEST_VVCFG( 81, 13, 0, 0x07, 64, 63 );
+  TEST_VVCFG( 82, 13, 0, 0x07, 62, 62 );
+
+  TEST_VVCFG( 83, 13, 0, 0xff, 168, 168 );
+  TEST_VVCFG( 84, 13, 0, 0xff, 169, 168 );
+  TEST_VVCFG( 85, 13, 0, 0xff, 167, 167 );
+
+  TEST_VVCFG( 86, 14, 0, 0x07, 57, 57 );
+  TEST_VVCFG( 87, 14, 0, 0x07, 58, 57 );
+  TEST_VVCFG( 88, 14, 0, 0x07, 56, 56 );
+
+  TEST_VVCFG( 89, 14, 0, 0xff, 152, 152 );
+  TEST_VVCFG( 90, 14, 0, 0xff, 153, 152 );
+  TEST_VVCFG( 91, 14, 0, 0xff, 151, 151 );
+
+  TEST_VVCFG( 92, 15, 0, 0x07, 54, 54 );
+  TEST_VVCFG( 93, 15, 0, 0x07, 55, 54 );
+  TEST_VVCFG( 94, 15, 0, 0x07, 53, 53 );
+
+  TEST_VVCFG( 95, 15, 0, 0xff, 144, 144 );
+  TEST_VVCFG( 96, 15, 0, 0xff, 145, 144 );
+  TEST_VVCFG( 97, 15, 0, 0xff, 143, 143 );
+
+  TEST_VVCFG( 98, 16, 0, 0x07, 51, 51 );
+  TEST_VVCFG( 99, 16, 0, 0x07, 52, 51 );
+  TEST_VVCFG( 100, 16, 0, 0x07, 50, 50 );
+
+  TEST_VVCFG( 101, 16, 0, 0xff, 136, 136 );
+  TEST_VVCFG( 102, 16, 0, 0xff, 137, 136 );
+  TEST_VVCFG( 103, 16, 0, 0xff, 135, 135 );
+
+  TEST_VVCFG( 104, 17, 0, 0x07, 48, 48 );
+  TEST_VVCFG( 105, 17, 0, 0x07, 49, 48 );
+  TEST_VVCFG( 106, 17, 0, 0x07, 47, 47 );
+
+  TEST_VVCFG( 107, 17, 0, 0xff, 128, 128 );
+  TEST_VVCFG( 108, 17, 0, 0xff, 129, 128 );
+  TEST_VVCFG( 109, 17, 0, 0xff, 127, 127 );
+
+  TEST_VVCFG( 110, 18, 0, 0x07, 45, 45 );
+  TEST_VVCFG( 111, 18, 0, 0x07, 46, 45 );
+  TEST_VVCFG( 112, 18, 0, 0x07, 44, 44 );
+
+  TEST_VVCFG( 113, 18, 0, 0xff, 120, 120 );
+  TEST_VVCFG( 114, 18, 0, 0xff, 121, 120 );
+  TEST_VVCFG( 115, 18, 0, 0xff, 119, 119 );
+
+  TEST_VVCFG( 116, 19, 0, 0x07, 42, 42 );
+  TEST_VVCFG( 117, 19, 0, 0x07, 43, 42 );
+  TEST_VVCFG( 118, 19, 0, 0x07, 41, 41 );
+
+  TEST_VVCFG( 119, 19, 0, 0xff, 112, 112 );
+  TEST_VVCFG( 120, 19, 0, 0xff, 113, 112 );
+  TEST_VVCFG( 121, 19, 0, 0xff, 111, 111 );
+
+  TEST_VVCFG( 122, 20, 0, 0x07, 39, 39 );
+  TEST_VVCFG( 123, 20, 0, 0x07, 40, 39 );
+  TEST_VVCFG( 124, 20, 0, 0x07, 38, 38 );
+
+  TEST_VVCFG( 125, 20, 0, 0xff, 104, 104 );
+  TEST_VVCFG( 126, 20, 0, 0xff, 105, 104 );
+  TEST_VVCFG( 127, 20, 0, 0xff, 103, 103 );
+
+  TEST_VVCFG( 128, 21, 0, 0x07, 36, 36 );
+  TEST_VVCFG( 129, 21, 0, 0x07, 37, 36 );
+  TEST_VVCFG( 130, 21, 0, 0x07, 35, 35 );
+
+  TEST_VVCFG( 131, 21, 0, 0xff, 96, 96 );
+  TEST_VVCFG( 132, 21, 0, 0xff, 97, 96 );
+  TEST_VVCFG( 133, 21, 0, 0xff, 95, 95 );
+
+  TEST_VVCFG( 134, 22, 0, 0x07, 36, 36 );
+  TEST_VVCFG( 135, 22, 0, 0x07, 37, 36 );
+  TEST_VVCFG( 136, 22, 0, 0x07, 35, 35 );
+
+  TEST_VVCFG( 137, 22, 0, 0xff, 96, 96 );
+  TEST_VVCFG( 138, 22, 0, 0xff, 97, 96 );
+  TEST_VVCFG( 139, 22, 0, 0xff, 95, 95 );
+
+  TEST_VVCFG( 140, 23, 0, 0x07, 33, 33 );
+  TEST_VVCFG( 141, 23, 0, 0x07, 34, 33 );
+  TEST_VVCFG( 142, 23, 0, 0x07, 32, 32 );
+
+  TEST_VVCFG( 143, 23, 0, 0xff, 88, 88 );
+  TEST_VVCFG( 144, 23, 0, 0xff, 89, 88 );
+  TEST_VVCFG( 145, 23, 0, 0xff, 87, 87 );
+
+  TEST_VVCFG( 146, 24, 0, 0x07, 33, 33 );
+  TEST_VVCFG( 147, 24, 0, 0x07, 34, 33 );
+  TEST_VVCFG( 148, 24, 0, 0x07, 32, 32 );
+
+  TEST_VVCFG( 149, 24, 0, 0xff, 88, 88 );
+  TEST_VVCFG( 150, 24, 0, 0xff, 89, 88 );
+  TEST_VVCFG( 151, 24, 0, 0xff, 87, 87 );
+
+  TEST_VVCFG( 152, 25, 0, 0x07, 30, 30 );
+  TEST_VVCFG( 153, 25, 0, 0x07, 31, 30 );
+  TEST_VVCFG( 154, 25, 0, 0x07, 29, 29 );
+
+  TEST_VVCFG( 155, 25, 0, 0xff, 80, 80 );
+  TEST_VVCFG( 156, 25, 0, 0xff, 81, 80 );
+  TEST_VVCFG( 157, 25, 0, 0xff, 79, 79 );
+
+  TEST_VVCFG( 158, 26, 0, 0x07, 30, 30 );
+  TEST_VVCFG( 159, 26, 0, 0x07, 31, 30 );
+  TEST_VVCFG( 160, 26, 0, 0x07, 29, 29 );
+
+  TEST_VVCFG( 161, 26, 0, 0xff, 80, 80 );
+  TEST_VVCFG( 162, 26, 0, 0xff, 81, 80 );
+  TEST_VVCFG( 163, 26, 0, 0xff, 79, 79 );
+
+  TEST_VVCFG( 164, 27, 0, 0x07, 27, 27 );
+  TEST_VVCFG( 165, 27, 0, 0x07, 28, 27 );
+  TEST_VVCFG( 166, 27, 0, 0x07, 26, 26 );
+
+  TEST_VVCFG( 167, 27, 0, 0xff, 72, 72 );
+  TEST_VVCFG( 168, 27, 0, 0xff, 73, 72 );
+  TEST_VVCFG( 169, 27, 0, 0xff, 71, 71 );
+
+  TEST_VVCFG( 170, 28, 0, 0x07, 27, 27 );
+  TEST_VVCFG( 171, 28, 0, 0x07, 28, 27 );
+  TEST_VVCFG( 172, 28, 0, 0x07, 26, 26 );
+
+  TEST_VVCFG( 173, 28, 0, 0xff, 72, 72 );
+  TEST_VVCFG( 174, 28, 0, 0xff, 73, 72 );
+  TEST_VVCFG( 175, 28, 0, 0xff, 71, 71 );
+
+  TEST_VVCFG( 176, 29, 0, 0x07, 27, 27 );
+  TEST_VVCFG( 177, 29, 0, 0x07, 28, 27 );
+  TEST_VVCFG( 178, 29, 0, 0x07, 26, 26 );
+
+  TEST_VVCFG( 179, 29, 0, 0xff, 72, 72 );
+  TEST_VVCFG( 180, 29, 0, 0xff, 73, 72 );
+  TEST_VVCFG( 181, 29, 0, 0xff, 71, 71 );
+
+  TEST_VVCFG( 182, 30, 0, 0x07, 24, 24 );
+  TEST_VVCFG( 183, 30, 0, 0x07, 25, 24 );
+  TEST_VVCFG( 184, 30, 0, 0x07, 23, 23 );
+
+  TEST_VVCFG( 185, 30, 0, 0xff, 64, 64 );
+  TEST_VVCFG( 186, 30, 0, 0xff, 65, 64 );
+  TEST_VVCFG( 187, 30, 0, 0xff, 63, 63 );
+
+  TEST_VVCFG( 188, 31, 0, 0x07, 24, 24 );
+  TEST_VVCFG( 189, 31, 0, 0x07, 25, 24 );
+  TEST_VVCFG( 190, 31, 0, 0x07, 23, 23 );
+
+  TEST_VVCFG( 191, 31, 0, 0xff, 64, 64 );
+  TEST_VVCFG( 192, 31, 0, 0xff, 65, 64 );
+  TEST_VVCFG( 193, 31, 0, 0xff, 63, 63 );
+
+  TEST_VVCFG( 194, 32, 0, 0x07, 24, 24 );
+  TEST_VVCFG( 195, 32, 0, 0x07, 25, 24 );
+  TEST_VVCFG( 196, 32, 0, 0x07, 23, 23 );
+
+  TEST_VVCFG( 197, 32, 0, 0xff, 64, 64 );
+  TEST_VVCFG( 198, 32, 0, 0xff, 65, 64 );
+  TEST_VVCFG( 199, 32, 0, 0xff, 63, 63 );
+
+  TEST_VVCFG( 200, 32, 0, 0x07, 24, 24 );
+  TEST_VVCFG( 201, 32, 0, 0x07, 25, 24 );
+  TEST_VVCFG( 202, 32, 0, 0x07, 23, 23 );
+
+  TEST_VVCFG( 203, 32, 0, 0xff, 64, 64 );
+  TEST_VVCFG( 204, 32, 0, 0xff, 65, 64 );
+  TEST_VVCFG( 205, 32, 0, 0xff, 63, 63 );
+
+  TEST_VVCFG( 206, 32, 1, 0x07, 24, 24 );
+  TEST_VVCFG( 207, 32, 1, 0x07, 25, 24 );
+  TEST_VVCFG( 208, 32, 1, 0x07, 23, 23 );
+
+  TEST_VVCFG( 209, 32, 1, 0xff, 64, 64 );
+  TEST_VVCFG( 210, 32, 1, 0xff, 65, 64 );
+  TEST_VVCFG( 211, 32, 1, 0xff, 63, 63 );
+
+  TEST_VVCFG( 212, 32, 2, 0x07, 21, 21 );
+  TEST_VVCFG( 213, 32, 2, 0x07, 22, 21 );
+  TEST_VVCFG( 214, 32, 2, 0x07, 20, 20 );
+
+  TEST_VVCFG( 215, 32, 2, 0xff, 56, 56 );
+  TEST_VVCFG( 216, 32, 2, 0xff, 57, 56 );
+  TEST_VVCFG( 217, 32, 2, 0xff, 55, 55 );
+
+  TEST_VVCFG( 218, 32, 3, 0x07, 21, 21 );
+  TEST_VVCFG( 219, 32, 3, 0x07, 22, 21 );
+  TEST_VVCFG( 220, 32, 3, 0x07, 20, 20 );
+
+  TEST_VVCFG( 221, 32, 3, 0xff, 56, 56 );
+  TEST_VVCFG( 222, 32, 3, 0xff, 57, 56 );
+  TEST_VVCFG( 223, 32, 3, 0xff, 55, 55 );
+
+  TEST_VVCFG( 224, 32, 4, 0x07, 21, 21 );
+  TEST_VVCFG( 225, 32, 4, 0x07, 22, 21 );
+  TEST_VVCFG( 226, 32, 4, 0x07, 20, 20 );
+
+  TEST_VVCFG( 227, 32, 4, 0xff, 56, 56 );
+  TEST_VVCFG( 228, 32, 4, 0xff, 57, 56 );
+  TEST_VVCFG( 229, 32, 4, 0xff, 55, 55 );
+
+  TEST_VVCFG( 230, 32, 5, 0x07, 21, 21 );
+  TEST_VVCFG( 231, 32, 5, 0x07, 22, 21 );
+  TEST_VVCFG( 232, 32, 5, 0x07, 20, 20 );
+
+  TEST_VVCFG( 233, 32, 5, 0xff, 56, 56 );
+  TEST_VVCFG( 234, 32, 5, 0xff, 57, 56 );
+  TEST_VVCFG( 235, 32, 5, 0xff, 55, 55 );
+
+  TEST_VVCFG( 236, 32, 6, 0x07, 18, 18 );
+  TEST_VVCFG( 237, 32, 6, 0x07, 19, 18 );
+  TEST_VVCFG( 238, 32, 6, 0x07, 17, 17 );
+
+  TEST_VVCFG( 239, 32, 6, 0xff, 48, 48 );
+  TEST_VVCFG( 240, 32, 6, 0xff, 49, 48 );
+  TEST_VVCFG( 241, 32, 6, 0xff, 47, 47 );
+
+  TEST_VVCFG( 242, 32, 7, 0x07, 18, 18 );
+  TEST_VVCFG( 243, 32, 7, 0x07, 19, 18 );
+  TEST_VVCFG( 244, 32, 7, 0x07, 17, 17 );
+
+  TEST_VVCFG( 245, 32, 7, 0xff, 48, 48 );
+  TEST_VVCFG( 246, 32, 7, 0xff, 49, 48 );
+  TEST_VVCFG( 247, 32, 7, 0xff, 47, 47 );
+
+  TEST_VVCFG( 248, 32, 8, 0x07, 18, 18 );
+  TEST_VVCFG( 249, 32, 8, 0x07, 19, 18 );
+  TEST_VVCFG( 250, 32, 8, 0x07, 17, 17 );
+
+  TEST_VVCFG( 251, 32, 8, 0xff, 48, 48 );
+  TEST_VVCFG( 252, 32, 8, 0xff, 49, 48 );
+  TEST_VVCFG( 253, 32, 8, 0xff, 47, 47 );
+
+  TEST_VVCFG( 254, 32, 9, 0x07, 18, 18 );
+  TEST_VVCFG( 255, 32, 9, 0x07, 19, 18 );
+  TEST_VVCFG( 256, 32, 9, 0x07, 17, 17 );
+
+  TEST_VVCFG( 257, 32, 9, 0xff, 48, 48 );
+  TEST_VVCFG( 258, 32, 9, 0xff, 49, 48 );
+  TEST_VVCFG( 259, 32, 9, 0xff, 47, 47 );
+
+  TEST_VVCFG( 260, 32, 10, 0x07, 18, 18 );
+  TEST_VVCFG( 261, 32, 10, 0x07, 19, 18 );
+  TEST_VVCFG( 262, 32, 10, 0x07, 17, 17 );
+
+  TEST_VVCFG( 263, 32, 10, 0xff, 48, 48 );
+  TEST_VVCFG( 264, 32, 10, 0xff, 49, 48 );
+  TEST_VVCFG( 265, 32, 10, 0xff, 47, 47 );
+
+  TEST_VVCFG( 266, 32, 11, 0x07, 18, 18 );
+  TEST_VVCFG( 267, 32, 11, 0x07, 19, 18 );
+  TEST_VVCFG( 268, 32, 11, 0x07, 17, 17 );
+
+  TEST_VVCFG( 269, 32, 11, 0xff, 48, 48 );
+  TEST_VVCFG( 270, 32, 11, 0xff, 49, 48 );
+  TEST_VVCFG( 271, 32, 11, 0xff, 47, 47 );
+
+  TEST_VVCFG( 272, 32, 12, 0x07, 15, 15 );
+  TEST_VVCFG( 273, 32, 12, 0x07, 16, 15 );
+  TEST_VVCFG( 274, 32, 12, 0x07, 14, 14 );
+
+  TEST_VVCFG( 275, 32, 12, 0xff, 40, 40 );
+  TEST_VVCFG( 276, 32, 12, 0xff, 41, 40 );
+  TEST_VVCFG( 277, 32, 12, 0xff, 39, 39 );
+
+  TEST_VVCFG( 278, 32, 13, 0x07, 15, 15 );
+  TEST_VVCFG( 279, 32, 13, 0x07, 16, 15 );
+  TEST_VVCFG( 280, 32, 13, 0x07, 14, 14 );
+
+  TEST_VVCFG( 281, 32, 13, 0xff, 40, 40 );
+  TEST_VVCFG( 282, 32, 13, 0xff, 41, 40 );
+  TEST_VVCFG( 283, 32, 13, 0xff, 39, 39 );
+
+  TEST_VVCFG( 284, 32, 14, 0x07, 15, 15 );
+  TEST_VVCFG( 285, 32, 14, 0x07, 16, 15 );
+  TEST_VVCFG( 286, 32, 14, 0x07, 14, 14 );
+
+  TEST_VVCFG( 287, 32, 14, 0xff, 40, 40 );
+  TEST_VVCFG( 288, 32, 14, 0xff, 41, 40 );
+  TEST_VVCFG( 289, 32, 14, 0xff, 39, 39 );
+
+  TEST_VVCFG( 290, 32, 15, 0x07, 15, 15 );
+  TEST_VVCFG( 291, 32, 15, 0x07, 16, 15 );
+  TEST_VVCFG( 292, 32, 15, 0x07, 14, 14 );
+
+  TEST_VVCFG( 293, 32, 15, 0xff, 40, 40 );
+  TEST_VVCFG( 294, 32, 15, 0xff, 41, 40 );
+  TEST_VVCFG( 295, 32, 15, 0xff, 39, 39 );
+
+  TEST_VVCFG( 296, 32, 16, 0x07, 15, 15 );
+  TEST_VVCFG( 297, 32, 16, 0x07, 16, 15 );
+  TEST_VVCFG( 298, 32, 16, 0x07, 14, 14 );
+
+  TEST_VVCFG( 299, 32, 16, 0xff, 40, 40 );
+  TEST_VVCFG( 300, 32, 16, 0xff, 41, 40 );
+  TEST_VVCFG( 301, 32, 16, 0xff, 39, 39 );
+
+  TEST_VVCFG( 302, 32, 17, 0x07, 15, 15 );
+  TEST_VVCFG( 303, 32, 17, 0x07, 16, 15 );
+  TEST_VVCFG( 304, 32, 17, 0x07, 14, 14 );
+
+  TEST_VVCFG( 305, 32, 17, 0xff, 40, 40 );
+  TEST_VVCFG( 306, 32, 17, 0xff, 41, 40 );
+  TEST_VVCFG( 307, 32, 17, 0xff, 39, 39 );
+
+  TEST_VVCFG( 308, 32, 18, 0x07, 15, 15 );
+  TEST_VVCFG( 309, 32, 18, 0x07, 16, 15 );
+  TEST_VVCFG( 310, 32, 18, 0x07, 14, 14 );
+
+  TEST_VVCFG( 311, 32, 18, 0xff, 40, 40 );
+  TEST_VVCFG( 312, 32, 18, 0xff, 41, 40 );
+  TEST_VVCFG( 313, 32, 18, 0xff, 39, 39 );
+
+  TEST_VVCFG( 314, 32, 19, 0x07, 15, 15 );
+  TEST_VVCFG( 315, 32, 19, 0x07, 16, 15 );
+  TEST_VVCFG( 316, 32, 19, 0x07, 14, 14 );
+
+  TEST_VVCFG( 317, 32, 19, 0xff, 40, 40 );
+  TEST_VVCFG( 318, 32, 19, 0xff, 41, 40 );
+  TEST_VVCFG( 319, 32, 19, 0xff, 39, 39 );
+
+  TEST_VVCFG( 320, 32, 20, 0x07, 15, 15 );
+  TEST_VVCFG( 321, 32, 20, 0x07, 16, 15 );
+  TEST_VVCFG( 322, 32, 20, 0x07, 14, 14 );
+
+  TEST_VVCFG( 323, 32, 20, 0xff, 40, 40 );
+  TEST_VVCFG( 324, 32, 20, 0xff, 41, 40 );
+  TEST_VVCFG( 325, 32, 20, 0xff, 39, 39 );
+
+  TEST_VVCFG( 326, 32, 21, 0x07, 12, 12 );
+  TEST_VVCFG( 327, 32, 21, 0x07, 13, 12 );
+  TEST_VVCFG( 328, 32, 21, 0x07, 11, 11 );
+
+  TEST_VVCFG( 329, 32, 21, 0xff, 32, 32 );
+  TEST_VVCFG( 330, 32, 21, 0xff, 33, 32 );
+  TEST_VVCFG( 331, 32, 21, 0xff, 31, 31 );
+
+  TEST_VVCFG( 332, 32, 22, 0x07, 12, 12 );
+  TEST_VVCFG( 333, 32, 22, 0x07, 13, 12 );
+  TEST_VVCFG( 334, 32, 22, 0x07, 11, 11 );
+
+  TEST_VVCFG( 335, 32, 22, 0xff, 32, 32 );
+  TEST_VVCFG( 336, 32, 22, 0xff, 33, 32 );
+  TEST_VVCFG( 337, 32, 22, 0xff, 31, 31 );
+
+  TEST_VVCFG( 338, 32, 23, 0x07, 12, 12 );
+  TEST_VVCFG( 339, 32, 23, 0x07, 13, 12 );
+  TEST_VVCFG( 340, 32, 23, 0x07, 11, 11 );
+
+  TEST_VVCFG( 341, 32, 23, 0xff, 32, 32 );
+  TEST_VVCFG( 342, 32, 23, 0xff, 33, 32 );
+  TEST_VVCFG( 343, 32, 23, 0xff, 31, 31 );
+
+  TEST_VVCFG( 344, 32, 24, 0x07, 12, 12 );
+  TEST_VVCFG( 345, 32, 24, 0x07, 13, 12 );
+  TEST_VVCFG( 346, 32, 24, 0x07, 11, 11 );
+
+  TEST_VVCFG( 347, 32, 24, 0xff, 32, 32 );
+  TEST_VVCFG( 348, 32, 24, 0xff, 33, 32 );
+  TEST_VVCFG( 349, 32, 24, 0xff, 31, 31 );
+
+  TEST_VVCFG( 350, 32, 25, 0x07, 12, 12 );
+  TEST_VVCFG( 351, 32, 25, 0x07, 13, 12 );
+  TEST_VVCFG( 352, 32, 25, 0x07, 11, 11 );
+
+  TEST_VVCFG( 353, 32, 25, 0xff, 32, 32 );
+  TEST_VVCFG( 354, 32, 25, 0xff, 33, 32 );
+  TEST_VVCFG( 355, 32, 25, 0xff, 31, 31 );
+
+  TEST_VVCFG( 356, 32, 26, 0x07, 12, 12 );
+  TEST_VVCFG( 357, 32, 26, 0x07, 13, 12 );
+  TEST_VVCFG( 358, 32, 26, 0x07, 11, 11 );
+
+  TEST_VVCFG( 359, 32, 26, 0xff, 32, 32 );
+  TEST_VVCFG( 360, 32, 26, 0xff, 33, 32 );
+  TEST_VVCFG( 361, 32, 26, 0xff, 31, 31 );
+
+  TEST_VVCFG( 362, 32, 27, 0x07, 12, 12 );
+  TEST_VVCFG( 363, 32, 27, 0x07, 13, 12 );
+  TEST_VVCFG( 364, 32, 27, 0x07, 11, 11 );
+
+  TEST_VVCFG( 365, 32, 27, 0xff, 32, 32 );
+  TEST_VVCFG( 366, 32, 27, 0xff, 33, 32 );
+  TEST_VVCFG( 367, 32, 27, 0xff, 31, 31 );
+
+  TEST_VVCFG( 368, 32, 28, 0x07, 12, 12 );
+  TEST_VVCFG( 369, 32, 28, 0x07, 13, 12 );
+  TEST_VVCFG( 370, 32, 28, 0x07, 11, 11 );
+
+  TEST_VVCFG( 371, 32, 28, 0xff, 32, 32 );
+  TEST_VVCFG( 372, 32, 28, 0xff, 33, 32 );
+  TEST_VVCFG( 373, 32, 28, 0xff, 31, 31 );
+
+  TEST_VVCFG( 374, 32, 29, 0x07, 12, 12 );
+  TEST_VVCFG( 375, 32, 29, 0x07, 13, 12 );
+  TEST_VVCFG( 376, 32, 29, 0x07, 11, 11 );
+
+  TEST_VVCFG( 377, 32, 29, 0xff, 32, 32 );
+  TEST_VVCFG( 378, 32, 29, 0xff, 33, 32 );
+  TEST_VVCFG( 379, 32, 29, 0xff, 31, 31 );
+
+  TEST_VVCFG( 380, 32, 30, 0x07, 12, 12 );
+  TEST_VVCFG( 381, 32, 30, 0x07, 13, 12 );
+  TEST_VVCFG( 382, 32, 30, 0x07, 11, 11 );
+
+  TEST_VVCFG( 383, 32, 30, 0xff, 32, 32 );
+  TEST_VVCFG( 384, 32, 30, 0xff, 33, 32 );
+  TEST_VVCFG( 385, 32, 30, 0xff, 31, 31 );
+
+  TEST_VVCFG( 386, 32, 31, 0x07, 12, 12 );
+  TEST_VVCFG( 387, 32, 31, 0x07, 13, 12 );
+  TEST_VVCFG( 388, 32, 31, 0x07, 11, 11 );
+
+  TEST_VVCFG( 389, 32, 31, 0xff, 32, 32 );
+  TEST_VVCFG( 390, 32, 31, 0xff, 33, 32 );
+  TEST_VVCFG( 391, 32, 31, 0xff, 31, 31 );
+
+  TEST_VVCFG( 392, 32, 32, 0x07, 12, 12 );
+  TEST_VVCFG( 393, 32, 32, 0x07, 13, 12 );
+  TEST_VVCFG( 394, 32, 32, 0x07, 11, 11 );
+
+  TEST_VVCFG( 395, 32, 32, 0xff, 32, 32 );
+  TEST_VVCFG( 396, 32, 32, 0xff, 33, 32 );
+  TEST_VVCFG( 397, 32, 32, 0xff, 31, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvcfgivl.S b/isa/rv64uv/vvcfgivl.S
new file mode 100644
index 0000000..83e4c1c
--- /dev/null
+++ b/isa/rv64uv/vvcfgivl.S
@@ -0,0 +1,559 @@
+#*****************************************************************************
+# vvcfgivl.S
+#-----------------------------------------------------------------------------
+#
+# Test vvcfgivl instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_VVCFGIVL( 2, 0, 0, 0x07, 768, 768 );
+  TEST_VVCFGIVL( 3, 0, 0, 0x07, 769, 768 );
+  TEST_VVCFGIVL( 4, 0, 0, 0x07, 767, 767 );
+
+  TEST_VVCFGIVL( 5, 0, 0, 0xff, 2048, 2048 );
+  TEST_VVCFGIVL( 6, 0, 0, 0xff, 2049, 2048 );
+  TEST_VVCFGIVL( 7, 0, 0, 0xff, 2047, 2047 );
+
+  TEST_VVCFGIVL( 8, 1, 0, 0x07, 768, 768 );
+  TEST_VVCFGIVL( 9, 1, 0, 0x07, 769, 768 );
+  TEST_VVCFGIVL( 10, 1, 0, 0x07, 767, 767 );
+
+  TEST_VVCFGIVL( 11, 1, 0, 0xff, 2048, 2048 );
+  TEST_VVCFGIVL( 12, 1, 0, 0xff, 2049, 2048 );
+  TEST_VVCFGIVL( 13, 1, 0, 0xff, 2047, 2047 );
+
+  TEST_VVCFGIVL( 14, 2, 0, 0x07, 768, 768 );
+  TEST_VVCFGIVL( 15, 2, 0, 0x07, 769, 768 );
+  TEST_VVCFGIVL( 16, 2, 0, 0x07, 767, 767 );
+
+  TEST_VVCFGIVL( 17, 2, 0, 0xff, 2048, 2048 );
+  TEST_VVCFGIVL( 18, 2, 0, 0xff, 2049, 2048 );
+  TEST_VVCFGIVL( 19, 2, 0, 0xff, 2047, 2047 );
+
+  TEST_VVCFGIVL( 20, 3, 0, 0x07, 384, 384 );
+  TEST_VVCFGIVL( 21, 3, 0, 0x07, 385, 384 );
+  TEST_VVCFGIVL( 22, 3, 0, 0x07, 383, 383 );
+
+  TEST_VVCFGIVL( 23, 3, 0, 0xff, 1024, 1024 );
+  TEST_VVCFGIVL( 24, 3, 0, 0xff, 1025, 1024 );
+  TEST_VVCFGIVL( 25, 3, 0, 0xff, 1023, 1023 );
+
+  TEST_VVCFGIVL( 26, 4, 0, 0x07, 255, 255 );
+  TEST_VVCFGIVL( 27, 4, 0, 0x07, 256, 255 );
+  TEST_VVCFGIVL( 28, 4, 0, 0x07, 254, 254 );
+
+  TEST_VVCFGIVL( 29, 4, 0, 0xff, 680, 680 );
+  TEST_VVCFGIVL( 30, 4, 0, 0xff, 681, 680 );
+  TEST_VVCFGIVL( 31, 4, 0, 0xff, 679, 679 );
+
+  TEST_VVCFGIVL( 32, 5, 0, 0x07, 192, 192 );
+  TEST_VVCFGIVL( 33, 5, 0, 0x07, 193, 192 );
+  TEST_VVCFGIVL( 34, 5, 0, 0x07, 191, 191 );
+
+  TEST_VVCFGIVL( 35, 5, 0, 0xff, 512, 512 );
+  TEST_VVCFGIVL( 36, 5, 0, 0xff, 513, 512 );
+  TEST_VVCFGIVL( 37, 5, 0, 0xff, 511, 511 );
+
+  TEST_VVCFGIVL( 38, 6, 0, 0x07, 153, 153 );
+  TEST_VVCFGIVL( 39, 6, 0, 0x07, 154, 153 );
+  TEST_VVCFGIVL( 40, 6, 0, 0x07, 152, 152 );
+
+  TEST_VVCFGIVL( 41, 6, 0, 0xff, 408, 408 );
+  TEST_VVCFGIVL( 42, 6, 0, 0xff, 409, 408 );
+  TEST_VVCFGIVL( 43, 6, 0, 0xff, 407, 407 );
+
+  TEST_VVCFGIVL( 44, 7, 0, 0x07, 126, 126 );
+  TEST_VVCFGIVL( 45, 7, 0, 0x07, 127, 126 );
+  TEST_VVCFGIVL( 46, 7, 0, 0x07, 125, 125 );
+
+  TEST_VVCFGIVL( 47, 7, 0, 0xff, 336, 336 );
+  TEST_VVCFGIVL( 48, 7, 0, 0xff, 337, 336 );
+  TEST_VVCFGIVL( 49, 7, 0, 0xff, 335, 335 );
+
+  TEST_VVCFGIVL( 50, 8, 0, 0x07, 108, 108 );
+  TEST_VVCFGIVL( 51, 8, 0, 0x07, 109, 108 );
+  TEST_VVCFGIVL( 52, 8, 0, 0x07, 107, 107 );
+
+  TEST_VVCFGIVL( 53, 8, 0, 0xff, 288, 288 );
+  TEST_VVCFGIVL( 54, 8, 0, 0xff, 289, 288 );
+  TEST_VVCFGIVL( 55, 8, 0, 0xff, 287, 287 );
+
+  TEST_VVCFGIVL( 56, 9, 0, 0x07, 96, 96 );
+  TEST_VVCFGIVL( 57, 9, 0, 0x07, 97, 96 );
+  TEST_VVCFGIVL( 58, 9, 0, 0x07, 95, 95 );
+
+  TEST_VVCFGIVL( 59, 9, 0, 0xff, 256, 256 );
+  TEST_VVCFGIVL( 60, 9, 0, 0xff, 257, 256 );
+  TEST_VVCFGIVL( 61, 9, 0, 0xff, 255, 255 );
+
+  TEST_VVCFGIVL( 62, 10, 0, 0x07, 84, 84 );
+  TEST_VVCFGIVL( 63, 10, 0, 0x07, 85, 84 );
+  TEST_VVCFGIVL( 64, 10, 0, 0x07, 83, 83 );
+
+  TEST_VVCFGIVL( 65, 10, 0, 0xff, 224, 224 );
+  TEST_VVCFGIVL( 66, 10, 0, 0xff, 225, 224 );
+  TEST_VVCFGIVL( 67, 10, 0, 0xff, 223, 223 );
+
+  TEST_VVCFGIVL( 68, 11, 0, 0x07, 75, 75 );
+  TEST_VVCFGIVL( 69, 11, 0, 0x07, 76, 75 );
+  TEST_VVCFGIVL( 70, 11, 0, 0x07, 74, 74 );
+
+  TEST_VVCFGIVL( 71, 11, 0, 0xff, 200, 200 );
+  TEST_VVCFGIVL( 72, 11, 0, 0xff, 201, 200 );
+  TEST_VVCFGIVL( 73, 11, 0, 0xff, 199, 199 );
+
+  TEST_VVCFGIVL( 74, 12, 0, 0x07, 69, 69 );
+  TEST_VVCFGIVL( 75, 12, 0, 0x07, 70, 69 );
+  TEST_VVCFGIVL( 76, 12, 0, 0x07, 68, 68 );
+
+  TEST_VVCFGIVL( 77, 12, 0, 0xff, 184, 184 );
+  TEST_VVCFGIVL( 78, 12, 0, 0xff, 185, 184 );
+  TEST_VVCFGIVL( 79, 12, 0, 0xff, 183, 183 );
+
+  TEST_VVCFGIVL( 80, 13, 0, 0x07, 63, 63 );
+  TEST_VVCFGIVL( 81, 13, 0, 0x07, 64, 63 );
+  TEST_VVCFGIVL( 82, 13, 0, 0x07, 62, 62 );
+
+  TEST_VVCFGIVL( 83, 13, 0, 0xff, 168, 168 );
+  TEST_VVCFGIVL( 84, 13, 0, 0xff, 169, 168 );
+  TEST_VVCFGIVL( 85, 13, 0, 0xff, 167, 167 );
+
+  TEST_VVCFGIVL( 86, 14, 0, 0x07, 57, 57 );
+  TEST_VVCFGIVL( 87, 14, 0, 0x07, 58, 57 );
+  TEST_VVCFGIVL( 88, 14, 0, 0x07, 56, 56 );
+
+  TEST_VVCFGIVL( 89, 14, 0, 0xff, 152, 152 );
+  TEST_VVCFGIVL( 90, 14, 0, 0xff, 153, 152 );
+  TEST_VVCFGIVL( 91, 14, 0, 0xff, 151, 151 );
+
+  TEST_VVCFGIVL( 92, 15, 0, 0x07, 54, 54 );
+  TEST_VVCFGIVL( 93, 15, 0, 0x07, 55, 54 );
+  TEST_VVCFGIVL( 94, 15, 0, 0x07, 53, 53 );
+
+  TEST_VVCFGIVL( 95, 15, 0, 0xff, 144, 144 );
+  TEST_VVCFGIVL( 96, 15, 0, 0xff, 145, 144 );
+  TEST_VVCFGIVL( 97, 15, 0, 0xff, 143, 143 );
+
+  TEST_VVCFGIVL( 98, 16, 0, 0x07, 51, 51 );
+  TEST_VVCFGIVL( 99, 16, 0, 0x07, 52, 51 );
+  TEST_VVCFGIVL( 100, 16, 0, 0x07, 50, 50 );
+
+  TEST_VVCFGIVL( 101, 16, 0, 0xff, 136, 136 );
+  TEST_VVCFGIVL( 102, 16, 0, 0xff, 137, 136 );
+  TEST_VVCFGIVL( 103, 16, 0, 0xff, 135, 135 );
+
+  TEST_VVCFGIVL( 104, 17, 0, 0x07, 48, 48 );
+  TEST_VVCFGIVL( 105, 17, 0, 0x07, 49, 48 );
+  TEST_VVCFGIVL( 106, 17, 0, 0x07, 47, 47 );
+
+  TEST_VVCFGIVL( 107, 17, 0, 0xff, 128, 128 );
+  TEST_VVCFGIVL( 108, 17, 0, 0xff, 129, 128 );
+  TEST_VVCFGIVL( 109, 17, 0, 0xff, 127, 127 );
+
+  TEST_VVCFGIVL( 110, 18, 0, 0x07, 45, 45 );
+  TEST_VVCFGIVL( 111, 18, 0, 0x07, 46, 45 );
+  TEST_VVCFGIVL( 112, 18, 0, 0x07, 44, 44 );
+
+  TEST_VVCFGIVL( 113, 18, 0, 0xff, 120, 120 );
+  TEST_VVCFGIVL( 114, 18, 0, 0xff, 121, 120 );
+  TEST_VVCFGIVL( 115, 18, 0, 0xff, 119, 119 );
+
+  TEST_VVCFGIVL( 116, 19, 0, 0x07, 42, 42 );
+  TEST_VVCFGIVL( 117, 19, 0, 0x07, 43, 42 );
+  TEST_VVCFGIVL( 118, 19, 0, 0x07, 41, 41 );
+
+  TEST_VVCFGIVL( 119, 19, 0, 0xff, 112, 112 );
+  TEST_VVCFGIVL( 120, 19, 0, 0xff, 113, 112 );
+  TEST_VVCFGIVL( 121, 19, 0, 0xff, 111, 111 );
+
+  TEST_VVCFGIVL( 122, 20, 0, 0x07, 39, 39 );
+  TEST_VVCFGIVL( 123, 20, 0, 0x07, 40, 39 );
+  TEST_VVCFGIVL( 124, 20, 0, 0x07, 38, 38 );
+
+  TEST_VVCFGIVL( 125, 20, 0, 0xff, 104, 104 );
+  TEST_VVCFGIVL( 126, 20, 0, 0xff, 105, 104 );
+  TEST_VVCFGIVL( 127, 20, 0, 0xff, 103, 103 );
+
+  TEST_VVCFGIVL( 128, 21, 0, 0x07, 36, 36 );
+  TEST_VVCFGIVL( 129, 21, 0, 0x07, 37, 36 );
+  TEST_VVCFGIVL( 130, 21, 0, 0x07, 35, 35 );
+
+  TEST_VVCFGIVL( 131, 21, 0, 0xff, 96, 96 );
+  TEST_VVCFGIVL( 132, 21, 0, 0xff, 97, 96 );
+  TEST_VVCFGIVL( 133, 21, 0, 0xff, 95, 95 );
+
+  TEST_VVCFGIVL( 134, 22, 0, 0x07, 36, 36 );
+  TEST_VVCFGIVL( 135, 22, 0, 0x07, 37, 36 );
+  TEST_VVCFGIVL( 136, 22, 0, 0x07, 35, 35 );
+
+  TEST_VVCFGIVL( 137, 22, 0, 0xff, 96, 96 );
+  TEST_VVCFGIVL( 138, 22, 0, 0xff, 97, 96 );
+  TEST_VVCFGIVL( 139, 22, 0, 0xff, 95, 95 );
+
+  TEST_VVCFGIVL( 140, 23, 0, 0x07, 33, 33 );
+  TEST_VVCFGIVL( 141, 23, 0, 0x07, 34, 33 );
+  TEST_VVCFGIVL( 142, 23, 0, 0x07, 32, 32 );
+
+  TEST_VVCFGIVL( 143, 23, 0, 0xff, 88, 88 );
+  TEST_VVCFGIVL( 144, 23, 0, 0xff, 89, 88 );
+  TEST_VVCFGIVL( 145, 23, 0, 0xff, 87, 87 );
+
+  TEST_VVCFGIVL( 146, 24, 0, 0x07, 33, 33 );
+  TEST_VVCFGIVL( 147, 24, 0, 0x07, 34, 33 );
+  TEST_VVCFGIVL( 148, 24, 0, 0x07, 32, 32 );
+
+  TEST_VVCFGIVL( 149, 24, 0, 0xff, 88, 88 );
+  TEST_VVCFGIVL( 150, 24, 0, 0xff, 89, 88 );
+  TEST_VVCFGIVL( 151, 24, 0, 0xff, 87, 87 );
+
+  TEST_VVCFGIVL( 152, 25, 0, 0x07, 30, 30 );
+  TEST_VVCFGIVL( 153, 25, 0, 0x07, 31, 30 );
+  TEST_VVCFGIVL( 154, 25, 0, 0x07, 29, 29 );
+
+  TEST_VVCFGIVL( 155, 25, 0, 0xff, 80, 80 );
+  TEST_VVCFGIVL( 156, 25, 0, 0xff, 81, 80 );
+  TEST_VVCFGIVL( 157, 25, 0, 0xff, 79, 79 );
+
+  TEST_VVCFGIVL( 158, 26, 0, 0x07, 30, 30 );
+  TEST_VVCFGIVL( 159, 26, 0, 0x07, 31, 30 );
+  TEST_VVCFGIVL( 160, 26, 0, 0x07, 29, 29 );
+
+  TEST_VVCFGIVL( 161, 26, 0, 0xff, 80, 80 );
+  TEST_VVCFGIVL( 162, 26, 0, 0xff, 81, 80 );
+  TEST_VVCFGIVL( 163, 26, 0, 0xff, 79, 79 );
+
+  TEST_VVCFGIVL( 164, 27, 0, 0x07, 27, 27 );
+  TEST_VVCFGIVL( 165, 27, 0, 0x07, 28, 27 );
+  TEST_VVCFGIVL( 166, 27, 0, 0x07, 26, 26 );
+
+  TEST_VVCFGIVL( 167, 27, 0, 0xff, 72, 72 );
+  TEST_VVCFGIVL( 168, 27, 0, 0xff, 73, 72 );
+  TEST_VVCFGIVL( 169, 27, 0, 0xff, 71, 71 );
+
+  TEST_VVCFGIVL( 170, 28, 0, 0x07, 27, 27 );
+  TEST_VVCFGIVL( 171, 28, 0, 0x07, 28, 27 );
+  TEST_VVCFGIVL( 172, 28, 0, 0x07, 26, 26 );
+
+  TEST_VVCFGIVL( 173, 28, 0, 0xff, 72, 72 );
+  TEST_VVCFGIVL( 174, 28, 0, 0xff, 73, 72 );
+  TEST_VVCFGIVL( 175, 28, 0, 0xff, 71, 71 );
+
+  TEST_VVCFGIVL( 176, 29, 0, 0x07, 27, 27 );
+  TEST_VVCFGIVL( 177, 29, 0, 0x07, 28, 27 );
+  TEST_VVCFGIVL( 178, 29, 0, 0x07, 26, 26 );
+
+  TEST_VVCFGIVL( 179, 29, 0, 0xff, 72, 72 );
+  TEST_VVCFGIVL( 180, 29, 0, 0xff, 73, 72 );
+  TEST_VVCFGIVL( 181, 29, 0, 0xff, 71, 71 );
+
+  TEST_VVCFGIVL( 182, 30, 0, 0x07, 24, 24 );
+  TEST_VVCFGIVL( 183, 30, 0, 0x07, 25, 24 );
+  TEST_VVCFGIVL( 184, 30, 0, 0x07, 23, 23 );
+
+  TEST_VVCFGIVL( 185, 30, 0, 0xff, 64, 64 );
+  TEST_VVCFGIVL( 186, 30, 0, 0xff, 65, 64 );
+  TEST_VVCFGIVL( 187, 30, 0, 0xff, 63, 63 );
+
+  TEST_VVCFGIVL( 188, 31, 0, 0x07, 24, 24 );
+  TEST_VVCFGIVL( 189, 31, 0, 0x07, 25, 24 );
+  TEST_VVCFGIVL( 190, 31, 0, 0x07, 23, 23 );
+
+  TEST_VVCFGIVL( 191, 31, 0, 0xff, 64, 64 );
+  TEST_VVCFGIVL( 192, 31, 0, 0xff, 65, 64 );
+  TEST_VVCFGIVL( 193, 31, 0, 0xff, 63, 63 );
+
+  TEST_VVCFGIVL( 194, 32, 0, 0x07, 24, 24 );
+  TEST_VVCFGIVL( 195, 32, 0, 0x07, 25, 24 );
+  TEST_VVCFGIVL( 196, 32, 0, 0x07, 23, 23 );
+
+  TEST_VVCFGIVL( 197, 32, 0, 0xff, 64, 64 );
+  TEST_VVCFGIVL( 198, 32, 0, 0xff, 65, 64 );
+  TEST_VVCFGIVL( 199, 32, 0, 0xff, 63, 63 );
+
+  TEST_VVCFGIVL( 200, 32, 0, 0x07, 24, 24 );
+  TEST_VVCFGIVL( 201, 32, 0, 0x07, 25, 24 );
+  TEST_VVCFGIVL( 202, 32, 0, 0x07, 23, 23 );
+
+  TEST_VVCFGIVL( 203, 32, 0, 0xff, 64, 64 );
+  TEST_VVCFGIVL( 204, 32, 0, 0xff, 65, 64 );
+  TEST_VVCFGIVL( 205, 32, 0, 0xff, 63, 63 );
+
+  TEST_VVCFGIVL( 206, 32, 1, 0x07, 24, 24 );
+  TEST_VVCFGIVL( 207, 32, 1, 0x07, 25, 24 );
+  TEST_VVCFGIVL( 208, 32, 1, 0x07, 23, 23 );
+
+  TEST_VVCFGIVL( 209, 32, 1, 0xff, 64, 64 );
+  TEST_VVCFGIVL( 210, 32, 1, 0xff, 65, 64 );
+  TEST_VVCFGIVL( 211, 32, 1, 0xff, 63, 63 );
+
+  TEST_VVCFGIVL( 212, 32, 2, 0x07, 21, 21 );
+  TEST_VVCFGIVL( 213, 32, 2, 0x07, 22, 21 );
+  TEST_VVCFGIVL( 214, 32, 2, 0x07, 20, 20 );
+
+  TEST_VVCFGIVL( 215, 32, 2, 0xff, 56, 56 );
+  TEST_VVCFGIVL( 216, 32, 2, 0xff, 57, 56 );
+  TEST_VVCFGIVL( 217, 32, 2, 0xff, 55, 55 );
+
+  TEST_VVCFGIVL( 218, 32, 3, 0x07, 21, 21 );
+  TEST_VVCFGIVL( 219, 32, 3, 0x07, 22, 21 );
+  TEST_VVCFGIVL( 220, 32, 3, 0x07, 20, 20 );
+
+  TEST_VVCFGIVL( 221, 32, 3, 0xff, 56, 56 );
+  TEST_VVCFGIVL( 222, 32, 3, 0xff, 57, 56 );
+  TEST_VVCFGIVL( 223, 32, 3, 0xff, 55, 55 );
+
+  TEST_VVCFGIVL( 224, 32, 4, 0x07, 21, 21 );
+  TEST_VVCFGIVL( 225, 32, 4, 0x07, 22, 21 );
+  TEST_VVCFGIVL( 226, 32, 4, 0x07, 20, 20 );
+
+  TEST_VVCFGIVL( 227, 32, 4, 0xff, 56, 56 );
+  TEST_VVCFGIVL( 228, 32, 4, 0xff, 57, 56 );
+  TEST_VVCFGIVL( 229, 32, 4, 0xff, 55, 55 );
+
+  TEST_VVCFGIVL( 230, 32, 5, 0x07, 21, 21 );
+  TEST_VVCFGIVL( 231, 32, 5, 0x07, 22, 21 );
+  TEST_VVCFGIVL( 232, 32, 5, 0x07, 20, 20 );
+
+  TEST_VVCFGIVL( 233, 32, 5, 0xff, 56, 56 );
+  TEST_VVCFGIVL( 234, 32, 5, 0xff, 57, 56 );
+  TEST_VVCFGIVL( 235, 32, 5, 0xff, 55, 55 );
+
+  TEST_VVCFGIVL( 236, 32, 6, 0x07, 18, 18 );
+  TEST_VVCFGIVL( 237, 32, 6, 0x07, 19, 18 );
+  TEST_VVCFGIVL( 238, 32, 6, 0x07, 17, 17 );
+
+  TEST_VVCFGIVL( 239, 32, 6, 0xff, 48, 48 );
+  TEST_VVCFGIVL( 240, 32, 6, 0xff, 49, 48 );
+  TEST_VVCFGIVL( 241, 32, 6, 0xff, 47, 47 );
+
+  TEST_VVCFGIVL( 242, 32, 7, 0x07, 18, 18 );
+  TEST_VVCFGIVL( 243, 32, 7, 0x07, 19, 18 );
+  TEST_VVCFGIVL( 244, 32, 7, 0x07, 17, 17 );
+
+  TEST_VVCFGIVL( 245, 32, 7, 0xff, 48, 48 );
+  TEST_VVCFGIVL( 246, 32, 7, 0xff, 49, 48 );
+  TEST_VVCFGIVL( 247, 32, 7, 0xff, 47, 47 );
+
+  TEST_VVCFGIVL( 248, 32, 8, 0x07, 18, 18 );
+  TEST_VVCFGIVL( 249, 32, 8, 0x07, 19, 18 );
+  TEST_VVCFGIVL( 250, 32, 8, 0x07, 17, 17 );
+
+  TEST_VVCFGIVL( 251, 32, 8, 0xff, 48, 48 );
+  TEST_VVCFGIVL( 252, 32, 8, 0xff, 49, 48 );
+  TEST_VVCFGIVL( 253, 32, 8, 0xff, 47, 47 );
+
+  TEST_VVCFGIVL( 254, 32, 9, 0x07, 18, 18 );
+  TEST_VVCFGIVL( 255, 32, 9, 0x07, 19, 18 );
+  TEST_VVCFGIVL( 256, 32, 9, 0x07, 17, 17 );
+
+  TEST_VVCFGIVL( 257, 32, 9, 0xff, 48, 48 );
+  TEST_VVCFGIVL( 258, 32, 9, 0xff, 49, 48 );
+  TEST_VVCFGIVL( 259, 32, 9, 0xff, 47, 47 );
+
+  TEST_VVCFGIVL( 260, 32, 10, 0x07, 18, 18 );
+  TEST_VVCFGIVL( 261, 32, 10, 0x07, 19, 18 );
+  TEST_VVCFGIVL( 262, 32, 10, 0x07, 17, 17 );
+
+  TEST_VVCFGIVL( 263, 32, 10, 0xff, 48, 48 );
+  TEST_VVCFGIVL( 264, 32, 10, 0xff, 49, 48 );
+  TEST_VVCFGIVL( 265, 32, 10, 0xff, 47, 47 );
+
+  TEST_VVCFGIVL( 266, 32, 11, 0x07, 18, 18 );
+  TEST_VVCFGIVL( 267, 32, 11, 0x07, 19, 18 );
+  TEST_VVCFGIVL( 268, 32, 11, 0x07, 17, 17 );
+
+  TEST_VVCFGIVL( 269, 32, 11, 0xff, 48, 48 );
+  TEST_VVCFGIVL( 270, 32, 11, 0xff, 49, 48 );
+  TEST_VVCFGIVL( 271, 32, 11, 0xff, 47, 47 );
+
+  TEST_VVCFGIVL( 272, 32, 12, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 273, 32, 12, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 274, 32, 12, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 275, 32, 12, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 276, 32, 12, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 277, 32, 12, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 278, 32, 13, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 279, 32, 13, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 280, 32, 13, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 281, 32, 13, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 282, 32, 13, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 283, 32, 13, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 284, 32, 14, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 285, 32, 14, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 286, 32, 14, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 287, 32, 14, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 288, 32, 14, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 289, 32, 14, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 290, 32, 15, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 291, 32, 15, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 292, 32, 15, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 293, 32, 15, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 294, 32, 15, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 295, 32, 15, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 296, 32, 16, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 297, 32, 16, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 298, 32, 16, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 299, 32, 16, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 300, 32, 16, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 301, 32, 16, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 302, 32, 17, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 303, 32, 17, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 304, 32, 17, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 305, 32, 17, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 306, 32, 17, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 307, 32, 17, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 308, 32, 18, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 309, 32, 18, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 310, 32, 18, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 311, 32, 18, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 312, 32, 18, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 313, 32, 18, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 314, 32, 19, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 315, 32, 19, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 316, 32, 19, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 317, 32, 19, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 318, 32, 19, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 319, 32, 19, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 320, 32, 20, 0x07, 15, 15 );
+  TEST_VVCFGIVL( 321, 32, 20, 0x07, 16, 15 );
+  TEST_VVCFGIVL( 322, 32, 20, 0x07, 14, 14 );
+
+  TEST_VVCFGIVL( 323, 32, 20, 0xff, 40, 40 );
+  TEST_VVCFGIVL( 324, 32, 20, 0xff, 41, 40 );
+  TEST_VVCFGIVL( 325, 32, 20, 0xff, 39, 39 );
+
+  TEST_VVCFGIVL( 326, 32, 21, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 327, 32, 21, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 328, 32, 21, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 329, 32, 21, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 330, 32, 21, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 331, 32, 21, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 332, 32, 22, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 333, 32, 22, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 334, 32, 22, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 335, 32, 22, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 336, 32, 22, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 337, 32, 22, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 338, 32, 23, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 339, 32, 23, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 340, 32, 23, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 341, 32, 23, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 342, 32, 23, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 343, 32, 23, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 344, 32, 24, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 345, 32, 24, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 346, 32, 24, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 347, 32, 24, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 348, 32, 24, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 349, 32, 24, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 350, 32, 25, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 351, 32, 25, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 352, 32, 25, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 353, 32, 25, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 354, 32, 25, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 355, 32, 25, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 356, 32, 26, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 357, 32, 26, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 358, 32, 26, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 359, 32, 26, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 360, 32, 26, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 361, 32, 26, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 362, 32, 27, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 363, 32, 27, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 364, 32, 27, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 365, 32, 27, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 366, 32, 27, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 367, 32, 27, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 368, 32, 28, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 369, 32, 28, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 370, 32, 28, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 371, 32, 28, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 372, 32, 28, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 373, 32, 28, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 374, 32, 29, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 375, 32, 29, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 376, 32, 29, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 377, 32, 29, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 378, 32, 29, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 379, 32, 29, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 380, 32, 30, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 381, 32, 30, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 382, 32, 30, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 383, 32, 30, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 384, 32, 30, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 385, 32, 30, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 386, 32, 31, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 387, 32, 31, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 388, 32, 31, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 389, 32, 31, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 390, 32, 31, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 391, 32, 31, 0xff, 31, 31 );
+
+  TEST_VVCFGIVL( 392, 32, 32, 0x07, 12, 12 );
+  TEST_VVCFGIVL( 393, 32, 32, 0x07, 13, 12 );
+  TEST_VVCFGIVL( 394, 32, 32, 0x07, 11, 11 );
+
+  TEST_VVCFGIVL( 395, 32, 32, 0xff, 32, 32 );
+  TEST_VVCFGIVL( 396, 32, 32, 0xff, 33, 32 );
+  TEST_VVCFGIVL( 397, 32, 32, 0xff, 31, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvmul_d.S b/isa/rv64uv/vvmul_d.S
new file mode 100644
index 0000000..9748fa4
--- /dev/null
+++ b/isa/rv64uv/vvmul_d.S
@@ -0,0 +1,73 @@
+#*****************************************************************************
+# vvmul_d.S
+#-----------------------------------------------------------------------------
+#
+# Test vvmul d.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  li a3,4
+  vvcfgivl a3,a3,32,0
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+  ld a1,0(a5)
+  li a2,4
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li a2,6
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li a2,6
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li a2,4
+  li x28,5
+  bne a1,a2,fail
+  j pass
+
+vtcode:
+  mul x2,x2,x3
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/wakeup.S b/isa/rv64uv/wakeup.S
new file mode 100644
index 0000000..62cc6c8
--- /dev/null
+++ b/isa/rv64uv/wakeup.S
@@ -0,0 +1,159 @@
+#*****************************************************************************
+# wakeup.S
+#-----------------------------------------------------------------------------
+#
+# Test wakeup.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  # make sure these don't choke at the beginning
+  fence.v.l
+  fence.v.l
+  fence.v.g
+  fence.v.g
+
+  # this shouldn't go through since app vl is zero
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,0xdeadbeefcafebabe
+  li x28,2
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,3
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,4
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,5
+  bne a1,a2,fail
+
+  # check default hw vector length, which is 32
+  li a3, 32
+  vsetvl a3, a3
+  li a0, 32
+  li x28, 6
+  bne a3, a0, fail
+
+  li a3, 33
+  vsetvl a3, a3
+  li a0, 32
+  li x28, 7
+  bne a3, a0, fail
+
+  li a3, 31
+  vsetvl a3, a3
+  li a0, 31
+  li x28, 8
+  bne a3, a0, fail
+
+  # now do some vector stuff without vvcfgivl
+  vsetvl x0, x0
+
+  li a3, 4
+  la a4,src1
+  la a5,src2
+  vsetvl a3, a3
+  vld vx2,a4
+  vld vx3,a5
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,5
+  li x28,9
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,10
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,11
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,12
+  bne a1,a2,fail
+
+  # initialize dest memory
+  li a3, 0xdeadbeefcafebabe
+  sd a3, 0(a5)
+  sd a3, 8(a5)
+  sd a3, 16(a5)
+  sd a3, 24(a5)
+
+  # test app vl zero again
+  li a3, 0
+  vsetvl a3, a3
+
+  la a3,src1
+  la a4,src2
+  vld vx2,a3
+  vld vx3,a4
+  lui a0,%hi(vtcode1)
+  vf %lo(vtcode1)(a0)
+  la a5,dest
+  vsd vx2,a5
+  fence.v.l
+
+  ld a1,0(a5)
+  li a2,0xdeadbeefcafebabe
+  li x28,13
+  bne a1,a2,fail
+  ld a1,8(a5)
+  li x28,14
+  bne a1,a2,fail
+  ld a1,16(a5)
+  li x28,15
+  bne a1,a2,fail
+  ld a1,24(a5)
+  li x28,16
+  bne a1,a2,fail
+
+  j pass
+
+vtcode1:
+  add x2,x2,x3
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+src1:
+  .dword 1
+  .dword 2
+  .dword 3
+  .dword 4
+src2:
+  .dword 4
+  .dword 3
+  .dword 2
+  .dword 1
+dest:
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+  .dword 0xdeadbeefcafebabe
+
+RVTEST_DATA_END