aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-09-27zicboz: comment # (#412)John Ingalls1-1/+1
2022-09-26zicbo test zero (#411)John Ingalls3-2/+49
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
These can change at any time and that is OK.
2022-07-22Fix string formatting in testlib.assertTrue()Tim Newsome1-1/+1
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
I don't have time to fix the bug right now, and nobody has run into the bug yet in any case.
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
Turn semihosting_fileio on for every hart. This test still fails if it ends up running on hart 1 instead of 0, but at least it's closer to passing. Feels like the remaining problem is in OpenOCD.
2022-07-01Complete this pass of pylint changes. (#401)Tim Newsome2-149/+151
2022-06-23Another pylint upgrade. (#398)Tim Newsome3-173/+191
* Another pylint upgrade. Lots of format string changes, which are more readable. More files to come... * Satisfy pylint for two more files.
2022-06-21Update information about Makefile fragments (#399)Mehmet Oguz Derin1-4/+2
The source of benchmarks' Makefile does not use fragments anymore. This commit removes the mention of them from the readme. Signed-off-by: Mehmet Oguz Derin <mehmetoguzderin@mehmetoguzderin.com>
2022-06-09Test misaligned stores. (#397)Tim Newsome8-0/+158
Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support).
2022-06-08Merge pull request #395 from riscv-software-src/misaligned_storeAndrew Waterman10-6/+164
Test misaligned stores
2022-06-08Test semihosting_fileioTim Newsome2-4/+27
In the original test, confirm that stdout data ends up in the OpenOCD log. In the new test, with `arm semihosting_fileio` enabled, confirm that stdout data ends up in gdb's CLI. This test requires https://github.com/riscv/riscv-openocd/pull/699.
2022-06-07Test misaligned loads.Tim Newsome8-0/+160
Cover lh, lw, and ld (only on rv64).
2022-06-07Set TESTNUM before executing code.Tim Newsome3-6/+4
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. Fix up shamt.S and csr.S to handle the new behavior.
2022-06-06Revert unaligned tests.Tim Newsome3-51/+1
They lead to two problems: 1. The change to set TESTNUM before the test instead of after broke a few tests that relied on the old behavior. 2. Some tests in the v variant do something in the exception handler such that when they get an unaligned access exception, they end up stuck in a loop of unaligned access exceptions and the exception handler set up in the test is never called.
2022-06-06Test unaligned ld accesses.Tim Newsome1-0/+27
Identical to the lw change in #391.
2022-06-06Add unaligned test cases for lwTim Newsome1-0/+23
The test passes if either the target register contains the correct value, or the target raises a misaligned load exception.
2022-06-06Set TESTNUM before executing code.Tim Newsome1-1/+1
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails.
2022-05-31Address pylint warnings. (#385)Tim Newsome8-15/+16
I'm running a newer version of pylint, and thus there are new warnings to be fixed. All very minor.
2022-05-31Fix GdbTest.disable_pmp failing on systems which support NAPOT but not TOR ↵Luke Wren1-2/+8
regions (#388)
2022-05-28Permit mtval to be zero in misaligned address test, fixes #389 (#390)Luke Wren1-0/+2
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
Adjust test to work with that.
2022-04-25Add EbreakTest. (#380)Tim Newsome2-0/+62
* Add EbreakTest. Confirm correct behavior when somebody bakes an ebreak instruction into their code. * Forgot to commit ebreak.c
2022-04-07Make download test data const. (#378)Tim Newsome1-2/+2
That way it can go into flash.
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
Otherwise, "make run" doesn't work.
2022-03-03With new OpenOCD, gdb prints thread info differently (#373)Tim Newsome1-1/+2
It includes the name in quotes: ```* 2 Thread 1 "Current Execution" (Name: Current Execution) 0x10000100 in main``` Just ignore that part.
2022-03-03Add assert to MemorySampleTest. (#370)Tim Newsome1-0/+1
Now it will give slightly more helpful output if it fails.
2022-02-09Debug test to check that stepping doesn't inappropriately switch to Thread 1 ↵Greg Savin1-0/+21
(#369)
2022-01-06Add gdb.interact() for debug tests. (#367)Tim Newsome1-0/+18
This feature lets you easily interact with the gdb after the test has run to a certain point.
2021-11-29Fix TranslateTests. (#365)Tim Newsome2-5/+7
They used to set U, A, D, in intermediate page table entries which is no longer allowed.
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
The tests don't confirm that the order actually changes, but at least the code that does the work now is executed during the tests.
2021-11-12Create DisconnectTest. (#364)Tim Newsome2-32/+53
Disconnects from gdb, and then reconnects, making sure that didn't change any of the registers. This test will start passing when https://github.com/riscv/riscv-openocd/pull/661 merges.
2021-11-12Add timing output to DebugTurboStep. (#362)Tim Newsome1-1/+5
Useful for estimating interactive performance.
2021-10-05Remove slen. (#360)Tim Newsome4-22/+16
It's not an argument to spike anymore. Also switch testing the vector unit from multi-gdb to `-rtos hwthread`. This exposes a bug in OpenOCD (which is already fixed).
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
Thanks to @pdonahue-ventana for pointing this out
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
...since not all implementations will support it
2021-07-19Bump envAndrew Waterman1-20/+0
Fixes #350
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
2021-06-29Update README.md (#342)mymatin1-1/+1
2021-06-08Tweaks for multispike. (#339)Tim Newsome3-9/+19
1. Don't run all tests in multi-spike. Extra coverage is negligible, and it just takes too long. 2. Increase a few timeouts.
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
There are two reasons that writing the cycle counter might trap: - Because it's a read-only CSR - Because mcounteren.CY=0 or scounteren.CY=0 We want to make sure we're testing the first property, so set up the other bits accordingly.
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome6-63/+70
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵SLAMET RIANTO2-0/+2
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵SLAMET RIANTO3-0/+52
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome9-40/+303
* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome9-15/+103
* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
generated by cgit v1.1 at 2024-07-18 04:28:42 +0000