aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2014-05-05unrolled clogMem and made minor tweak to sdisorderrekallDrew Zagieboylo2-7/+9
2014-05-04Merge branch 'rekall' of github.com:ucb-bar/riscv-tests into rekallDrew Zagieboylo1-2/+2
2014-05-04added funroll-loops to gcc compilerDrew Zagieboylo2-4/+4
2014-05-02Change stream_d.c define to make script workIsaac Wu1-2/+2
2014-05-01put clog mem into util.h and updated stream benchmarkDrew Zagieboylo3-15/+25
2014-05-01Merge branch 'rekall' of github.com:ucb-bar/riscv-tests into rekallDrew Zagieboylo16-0/+9057
2014-05-01increased stack size and added multi-core interferenceDrew Zagieboylo2-21/+41
2014-04-30Merge branch 'rekall' of github.com:ucb-bar/riscv-tests into rekallIsaac Wu1-5/+7
2014-04-30Added stream benchmark to testsIsaac Wu16-0/+9057
2014-04-28forced compiler to compile Chase methodDrew Zagieboylo1-5/+7
2014-04-19Added sdisorder to riscv-testsIsaac Wu3-0/+108
2014-04-14commit high-performance mm (scalar and vector versions)Yunsup Lee18-325/+847
2014-04-08Adjust hwacha misaligned instruction test to ignore lower 2 bits in compariso...Stephen Twigg1-0/+2
2014-04-07Resync env with riscv-opcodesStephen Twigg1-5/+5
2014-04-07Add radix sort benchmarkAndrew Waterman7-7/+379
2014-04-03setStats in benchmarks now should set and unset the stats register. Also, rem...Stephen Twigg2-5/+14
2014-04-03Sync env with opcodesStephen Twigg1-5/+5
2014-03-25Make qsort input size more reasonableAndrew Waterman1-1539/+105
2014-03-25Make qsort benchmark more meaningfulAndrew Waterman4-96/+1722
2014-03-18Check FP corner cases and flagsAndrew Waterman7-183/+210
2014-03-06Add fclass.{s|d} testAndrew Waterman2-1/+58
2014-03-03update envYunsup Lee1-5/+5
2014-03-02push envYunsup Lee1-5/+5
2014-03-02add vfmsv.{s,d} testsYunsup Lee3-5/+60
2014-02-27push envYunsup Lee1-5/+5
2014-02-27add keepcfg testYunsup Lee2-1/+84
2014-02-26test to see whether vector unit is able to take 2 fmas in parallelYunsup Lee2-1/+181
2014-02-25push envYunsup Lee1-5/+5
2014-02-22Sort fixes: support for repeated trials.Eric Love3-35/+65
2014-02-20Merge commit '0661b47765081c710af3df66ec698aa58ff14d5d'Eric Love6-0/+2501
2014-02-20Added TAV sort benchmarksEric Love6-0/+2501
2014-02-11Run benchmarks in user modeAndrew Waterman3-49/+186
2014-02-11Merge branch 'master' of github.com:ucb-bar/riscv-testsAdam Izraelevitz199-1298/+5346
2014-02-11Updated README to recursively initialize reposAdam Izraelevitz1-0/+1
2014-02-10Revert to old AUIPC definitionAndrew Waterman3-21/+13
2014-02-06with env as a submodule, now have to populate itScott Beamer1-0/+1
2014-02-06fix recursive interrupts, and more improvements to codeYunsup Lee1-5/+5
2014-02-06Improve VM trap entry codeAndrew Waterman1-5/+5
2014-02-06Clean up benchmarks; support uarch-specific countersAndrew Waterman31-1026/+352
2014-02-06push envYunsup Lee1-5/+5
2014-02-04Add Stephen's vector FFT codeQuan Nguyen17-1/+1164
2014-02-03Add vfmsv instruction test, change vsetprec to vsetucfgQuan Nguyen3-2/+58
2014-01-31Shrink hex dumpsAndrew Waterman27-28/+2
2014-01-31Add rv32si tests, including illegality of shamt[5]Andrew Waterman8-15/+95
2014-01-31Minor Makefile improvementsHenry Cook2-3/+3
2014-01-31Make CSR test much more robustAndrew Waterman1-0/+52
2014-01-31Reference TESTNUM instead of x28 directlyAndrew Waterman69-217/+217
2014-01-23Done with rv32ui asm test portsEric Love1-2/+2
2014-01-23Fixed srl, srliEric Love3-25/+35
2014-01-23srl and sraiEric Love3-33/+33
generated by cgit v1.1 at 2025-03-09 22:04:07 +0000