diff options
Diffstat (limited to 'isa/rv64mi')
-rw-r--r-- | isa/rv64mi/Makefrag | 3 | ||||
-rw-r--r-- | isa/rv64mi/sd-misaligned.S | 44 | ||||
-rw-r--r-- | isa/rv64mi/sh-misaligned.S | 38 | ||||
-rw-r--r-- | isa/rv64mi/sw-misaligned.S | 40 |
4 files changed, 125 insertions, 0 deletions
diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag index 2f88249..8e437e0 100644 --- a/isa/rv64mi/Makefrag +++ b/isa/rv64mi/Makefrag @@ -15,5 +15,8 @@ rv64mi_sc_tests = \ ld-misaligned \ lw-misaligned \ lh-misaligned \ + sh-misaligned \ + sw-misaligned \ + sd-misaligned \ rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) diff --git a/isa/rv64mi/sd-misaligned.S b/isa/rv64mi/sd-misaligned.S new file mode 100644 index 0000000..5f5a0b3 --- /dev/null +++ b/isa/rv64mi/sd-misaligned.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sd-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned stores work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_ST_OP( 2, ld, sd, 0x0102030405060708, 0, tdat ); + TEST_ST_OP( 3, ld, sd, 0x090a0b0c0d0e0f10, 1, tdat ); + TEST_ST_OP( 4, ld, sd, 0x1112131415161718, 2, tdat ); + TEST_ST_OP( 5, ld, sd, 0x191a1b1c1d1e1f20, 3, tdat ); + TEST_ST_OP( 6, ld, sd, 0x2122232425262728, 4, tdat ); + TEST_ST_OP( 7, ld, sd, 0x292a2b2c2d2e2f30, 5, tdat ); + TEST_ST_OP( 8, ld, sd, 0x3132333435363738, 6, tdat ); + TEST_ST_OP( 9, ld, sd, 0x393a3b3c3d3e3f40, 7, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_STORE_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .zero 16 + +RVTEST_DATA_END diff --git a/isa/rv64mi/sh-misaligned.S b/isa/rv64mi/sh-misaligned.S new file mode 100644 index 0000000..668c918 --- /dev/null +++ b/isa/rv64mi/sh-misaligned.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned stores work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_ST_OP( 2, lh, sh, 0x1234, 0, tdat ); + TEST_ST_OP( 3, lh, sh, 0x5678, 1, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_STORE_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .zero 4 + +RVTEST_DATA_END diff --git a/isa/rv64mi/sw-misaligned.S b/isa/rv64mi/sw-misaligned.S new file mode 100644 index 0000000..8da698b --- /dev/null +++ b/isa/rv64mi/sw-misaligned.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sw-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned stores work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_ST_OP( 2, lw, sw, 0x12345678, 0, tdat ); + TEST_ST_OP( 3, lw, sw, 0xffffffff9abcdef0, 1, tdat ); + TEST_ST_OP( 4, lw, sw, 0xffffffffdeadbeef, 2, tdat ); + TEST_ST_OP( 5, lw, sw, 0xfffffffffeed0011, 3, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_STORE_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .zero 8 + +RVTEST_DATA_END |