diff options
| -rw-r--r-- | isa/Makefile | 8 | ||||
| -rw-r--r-- | isa/rv32uzbs/Makefrag | 15 | ||||
| -rw-r--r-- | isa/rv32uzbs/bclr.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbs/bclri.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbs/bext.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbs/bexti.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbs/binv.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbs/binvi.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbs/bset.S | 7 | ||||
| -rw-r--r-- | isa/rv32uzbs/bseti.S | 7 | ||||
| -rw-r--r-- | isa/rv64uzbs/Makefrag | 15 | ||||
| -rw-r--r-- | isa/rv64uzbs/bclr.S | 96 | ||||
| -rw-r--r-- | isa/rv64uzbs/bclri.S | 74 | ||||
| -rw-r--r-- | isa/rv64uzbs/bext.S | 96 | ||||
| -rw-r--r-- | isa/rv64uzbs/bexti.S | 74 | ||||
| -rw-r--r-- | isa/rv64uzbs/binv.S | 96 | ||||
| -rw-r--r-- | isa/rv64uzbs/binvi.S | 75 | ||||
| -rw-r--r-- | isa/rv64uzbs/bset.S | 96 | ||||
| -rw-r--r-- | isa/rv64uzbs/bseti.S | 74 |
19 files changed, 773 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index cb790a0..bf85e1f 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -17,6 +17,7 @@ include $(src_dir)/rv64uzfh/Makefrag include $(src_dir)/rv64uzba/Makefrag include $(src_dir)/rv64uzbb/Makefrag include $(src_dir)/rv64uzbc/Makefrag +include $(src_dir)/rv64uzbs/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -32,6 +33,7 @@ include $(src_dir)/rv32uzfh/Makefrag include $(src_dir)/rv32uzba/Makefrag include $(src_dir)/rv32uzbb/Makefrag include $(src_dir)/rv32uzbc/Makefrag +include $(src_dir)/rv32uzbs/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -56,10 +58,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ define compile_template @@ -95,6 +97,7 @@ $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) $(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) $(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) $(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -108,6 +111,7 @@ $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) $(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) $(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64)) +$(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) diff --git a/isa/rv32uzbs/Makefrag b/isa/rv32uzbs/Makefrag new file mode 100644 index 0000000..7af7c42 --- /dev/null +++ b/isa/rv32uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv32uzbs tests +#----------------------------------------------------------------------- + +rv32uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv32uzbs_p_tests = $(addprefix rv32uzbs-p-, $(rv32uzbs_sc_tests)) +rv32uzbs_v_tests = $(addprefix rv32uzbs-v-, $(rv32uzbs_sc_tests)) +rv32uzbs_ps_tests = $(addprefix rv32uzbs-ps-, $(rv32uzbs_sc_tests)) + +spike_tests += $(rv32uzbs_p_tests) $(rv32uzbs_v_tests) diff --git a/isa/rv32uzbs/bclr.S b/isa/rv32uzbs/bclr.S new file mode 100644 index 0000000..10f7e50 --- /dev/null +++ b/isa/rv32uzbs/bclr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclr.S" diff --git a/isa/rv32uzbs/bclri.S b/isa/rv32uzbs/bclri.S new file mode 100644 index 0000000..2f709d8 --- /dev/null +++ b/isa/rv32uzbs/bclri.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclri.S" diff --git a/isa/rv32uzbs/bext.S b/isa/rv32uzbs/bext.S new file mode 100644 index 0000000..0f838e5 --- /dev/null +++ b/isa/rv32uzbs/bext.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bext.S" diff --git a/isa/rv32uzbs/bexti.S b/isa/rv32uzbs/bexti.S new file mode 100644 index 0000000..91ee2d6 --- /dev/null +++ b/isa/rv32uzbs/bexti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bexti.S" diff --git a/isa/rv32uzbs/binv.S b/isa/rv32uzbs/binv.S new file mode 100644 index 0000000..55ea39b --- /dev/null +++ b/isa/rv32uzbs/binv.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binv.S" diff --git a/isa/rv32uzbs/binvi.S b/isa/rv32uzbs/binvi.S new file mode 100644 index 0000000..5874363 --- /dev/null +++ b/isa/rv32uzbs/binvi.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binvi.S" diff --git a/isa/rv32uzbs/bset.S b/isa/rv32uzbs/bset.S new file mode 100644 index 0000000..4220823 --- /dev/null +++ b/isa/rv32uzbs/bset.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bset.S" diff --git a/isa/rv32uzbs/bseti.S b/isa/rv32uzbs/bseti.S new file mode 100644 index 0000000..4a6179e --- /dev/null +++ b/isa/rv32uzbs/bseti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bseti.S" diff --git a/isa/rv64uzbs/Makefrag b/isa/rv64uzbs/Makefrag new file mode 100644 index 0000000..3264b4d --- /dev/null +++ b/isa/rv64uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv64uzbs tests +#----------------------------------------------------------------------- + +rv64uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv64uzbs_p_tests = $(addprefix rv64uzbs-p-, $(rv64uzbs_sc_tests)) +rv64uzbs_v_tests = $(addprefix rv64uzbs-v-, $(rv64uzbs_sc_tests)) +rv64uzbs_ps_tests = $(addprefix rv64uzbs-ps-, $(rv64uzbs_sc_tests)) + +spike_tests += $(rv64uzbs_p_tests) $(rv64uzbs_v_tests) diff --git a/isa/rv64uzbs/bclr.S b/isa/rv64uzbs/bclr.S new file mode 100644 index 0000000..75d48de --- /dev/null +++ b/isa/rv64uzbs/bclr.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclr.S +#----------------------------------------------------------------------------- +# +# Test bclr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bclr, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bclr, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bclr, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bclr, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bclr, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bclr, 0x21212120, 0x21212121, 0 ); + TEST_RR_OP( 13, bclr, 0x21212121, 0x21212121, 1 ); + TEST_RR_OP( 14, bclr, 0x21212121, 0x21212121, 7 ); + TEST_RR_OP( 15, bclr, 0x21210121, 0x21212121, 13 ); + TEST_RR_OP( 16, bclr, 0x04848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bclr, 0x21212120, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bclr, 0x84848484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bclr, 0x4484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bclr, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bclr, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bclr, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bclr, 0x00000001, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bclr, 0x00001551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bclr, 3, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bclr, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bclr, 32, 32 ); + TEST_RR_ZEROSRC12( 42, bclr, 0 ); + TEST_RR_ZERODEST( 43, bclr, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bclri.S b/isa/rv64uzbs/bclri.S new file mode 100644 index 0000000..3d4fdf9 --- /dev/null +++ b/isa/rv64uzbs/bclri.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclri.S +#----------------------------------------------------------------------------- +# +# Test bclri instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bclri, 0xff00ff00, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bclri, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bclri, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bclri, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bclri, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bclri, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bclri, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bclri, 0x21212120, 0x21212121, 0 ); + TEST_IMM_OP( 13, bclri, 0x21212121, 0x21212121, 1 ); + TEST_IMM_OP( 14, bclri, 0x21212121, 0x21212121, 7 ); + TEST_IMM_OP( 15, bclri, 0x21210121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bclri, 0x04848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bclri, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bclri, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bclri, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bclri, 0x00000001, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bclri, 0, 31 ); + TEST_IMM_ZERODEST( 25, bclri, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bext.S b/isa/rv64uzbs/bext.S new file mode 100644 index 0000000..0440741 --- /dev/null +++ b/isa/rv64uzbs/bext.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bext.S +#----------------------------------------------------------------------------- +# +# Test bext instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bext, 0, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bext, 1, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bext, 1, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bext, 1, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bext, 1, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bext, 1, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bext, 1, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bext, 1, 0x21212121, 0 ); + TEST_RR_OP( 13, bext, 0, 0x21212121, 1 ); + TEST_RR_OP( 14, bext, 0, 0x21212121, 7 ); + TEST_RR_OP( 15, bext, 1, 0x21212121, 13 ); + TEST_RR_OP( 16, bext, 1, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bext, 1, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bext, 0, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bext, 0, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bext, 0, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bext, 1, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bext, 0, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bext, 1, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bext, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bext, 0, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bext, 1, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bext, 0, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bext, 1, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bext, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bext, 0, 32 ); + TEST_RR_ZEROSRC12( 42, bext, 0 ); + TEST_RR_ZERODEST( 43, bext, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bexti.S b/isa/rv64uzbs/bexti.S new file mode 100644 index 0000000..19c9ed5 --- /dev/null +++ b/isa/rv64uzbs/bexti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bexti.S +#----------------------------------------------------------------------------- +# +# Test bexti instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bexti, 0, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bexti, 1, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bexti, 1, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bexti, 1, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bexti, 1, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bexti, 1, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bexti, 1, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bexti, 1, 0x21212121, 0 ); + TEST_IMM_OP( 13, bexti, 0, 0x21212121, 1 ); + TEST_IMM_OP( 14, bexti, 0, 0x21212121, 7 ); + TEST_IMM_OP( 15, bexti, 1, 0x21212121, 13 ); + TEST_IMM_OP( 16, bexti, 1, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bexti, 0, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bexti, 1, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bexti, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bexti, 0, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bexti, 0, 31 ); + TEST_IMM_ZERODEST( 25, bexti, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/binv.S b/isa/rv64uzbs/binv.S new file mode 100644 index 0000000..853b398 --- /dev/null +++ b/isa/rv64uzbs/binv.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binv.S +#----------------------------------------------------------------------------- +# +# Test binv instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, binv, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, binv, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, binv, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, binv, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, binv, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, binv, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, binv, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, binv, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, binv, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, binv, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, binv, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, binv, 0x00000000a1212121, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, binv, 0x0000000021212120, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, binv, 0x0000000021212123, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, binv, 0x00000000212121a1, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, binv, 0x0000000021216121, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, binv, 0x8000000021212121, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, binv, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, binv, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, binv, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, binv, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, binv, 0x00004001, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, binv, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, binv, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, binv, 33, 32 ); + TEST_RR_ZEROSRC12( 42, binv, 1 ); + TEST_RR_ZERODEST( 43, binv, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/binvi.S b/isa/rv64uzbs/binvi.S new file mode 100644 index 0000000..07af1f4 --- /dev/null +++ b/isa/rv64uzbs/binvi.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binvi.S +#----------------------------------------------------------------------------- +# +# Test binvi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, binvi, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, binvi, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, binvi, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, binvi, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, binvi, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, binvi, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, binvi, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, binvi, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, binvi, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, binvi, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, binvi, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, binvi, 0x00000000a1212121, 0x0000000021212121, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, binvi, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, binvi, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, binvi, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, binvi, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + + TEST_IMM_ZEROSRC1( 24, binvi, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, binvi, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bset.S b/isa/rv64uzbs/bset.S new file mode 100644 index 0000000..ee80b60 --- /dev/null +++ b/isa/rv64uzbs/bset.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_RR_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_RR_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_RR_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bset, 0x21212121, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bset, 0x21212123, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bset, 0x212121a1, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bset, 0x8484c484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bset, 0xc484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bset, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bset, 0x00005551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bset, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bset, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, bset, 33, 32 ); + TEST_RR_ZEROSRC12( 42, bset, 1 ); + TEST_RR_ZERODEST( 43, bset, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bseti.S b/isa/rv64uzbs/bseti.S new file mode 100644 index 0000000..35a5501 --- /dev/null +++ b/isa/rv64uzbs/bseti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_IMM_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_IMM_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bset, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_DEST_BYPASS( 19, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_DEST_BYPASS( 20, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bset, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, bset, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |