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author | Tim Newsome <tim@sifive.com> | 2022-06-03 13:12:01 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-06-06 09:05:26 -0700 |
commit | 27dbc399e23d5f9668363706accc76911d6d31fc (patch) | |
tree | 5c3138e974f883a06f5d4117f258c608bc29ea9b /isa/rv64ui | |
parent | c91d26c50725a6eb3bcff2b01d4c65eba2f82541 (diff) | |
download | riscv-tests-27dbc399e23d5f9668363706accc76911d6d31fc.zip riscv-tests-27dbc399e23d5f9668363706accc76911d6d31fc.tar.gz riscv-tests-27dbc399e23d5f9668363706accc76911d6d31fc.tar.bz2 |
Revert unaligned tests.
They lead to two problems:
1. The change to set TESTNUM before the test instead of after broke a
few tests that relied on the old behavior.
2. Some tests in the v variant do something in the exception handler
such that when they get an unaligned access exception, they end up
stuck in a loop of unaligned access exceptions and the exception
handler set up in the test is never called.
Diffstat (limited to 'isa/rv64ui')
-rw-r--r-- | isa/rv64ui/ld.S | 27 | ||||
-rw-r--r-- | isa/rv64ui/lw.S | 23 |
2 files changed, 0 insertions, 50 deletions
diff --git a/isa/rv64ui/ld.S b/isa/rv64ui/ld.S index 341122e..948c34b 100644 --- a/isa/rv64ui/ld.S +++ b/isa/rv64ui/ld.S @@ -74,35 +74,8 @@ RVTEST_CODE_BEGIN li x2, 2; \ ) - # Test unaligned accesses, if the target supports them. - # Assume little-endian - TEST_LD_OP( 1000, ld, 0x00ff00ff00ff00ff, 0, tdat ); - TEST_LD_OP( 1001, ld, 0x0000ff00ff00ff00, 1, tdat ); - TEST_LD_OP( 1002, ld, 0xff0000ff00ff00ff, 2, tdat ); - TEST_LD_OP( 1003, ld, 0x00ff0000ff00ff00, 3, tdat ); - TEST_LD_OP( 1004, ld, 0xff00ff0000ff00ff, 4, tdat ); - TEST_LD_OP( 1005, ld, 0x00ff00ff0000ff00, 5, tdat ); - TEST_LD_OP( 1006, ld, 0xff00ff00ff0000ff, 6, tdat ); - TEST_LD_OP( 1007, ld, 0x00ff00ff00ff0000, 7, tdat ); - -skip_unaligned_tests: TEST_PASSFAIL - .align 2 - .global mtvec_handler -mtvec_handler: - # Only unaligned access tests should trap - li t0, 1000 - blt TESTNUM, t0, fail - - li t0, CAUSE_MISALIGNED_LOAD - csrr t1, mcause - bne t0, t1, fail - - la t0, skip_unaligned_tests - csrw mepc, t0 - mret - RVTEST_CODE_END .data diff --git a/isa/rv64ui/lw.S b/isa/rv64ui/lw.S index bb1cbb4..40a73f1 100644 --- a/isa/rv64ui/lw.S +++ b/isa/rv64ui/lw.S @@ -74,31 +74,8 @@ RVTEST_CODE_BEGIN li x2, 2; \ ) - # Test unaligned accesses, if the target supports them. - # Assume little-endian - TEST_LD_OP( 1000, lw, 0x0000000000ff00ff, 0, tdat ); - TEST_LD_OP( 1001, lw, 0x000000000000ff00, 1, tdat ); - TEST_LD_OP( 1002, lw, 0xffffffffff0000ff, 2, tdat ); - TEST_LD_OP( 1003, lw, 0x0000000000ff0000, 3, tdat ); - -skip_unaligned_tests: TEST_PASSFAIL - .align 2 - .global mtvec_handler -mtvec_handler: - # Only unaligned access tests should trap - li t0, 1000 - blt TESTNUM, t0, fail - - li t0, CAUSE_MISALIGNED_LOAD - csrr t1, mcause - bne t0, t1, fail - - la t0, skip_unaligned_tests - csrw mepc, t0 - mret - RVTEST_CODE_END .data |