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| author | Tommy Thorn <tommy-git@thorn.ws> | 2018-09-08 09:00:04 -0700 |
|---|---|---|
| committer | Tommy Thorn <tommy-git@thorn.ws> | 2018-09-08 09:13:11 -0700 |
| commit | ab4f35d0300e5dcfc62837d79b0c59d309f2ebfc (patch) | |
| tree | 1f9a771dd305e03bd4b6efee92c50952f01c4524 /isa/rv64ui/srlw.S | |
| parent | 9d3bc86d85d935f498065d54ead7e568f03b2824 (diff) | |
| download | riscv-tests-ab4f35d0300e5dcfc62837d79b0c59d309f2ebfc.zip riscv-tests-ab4f35d0300e5dcfc62837d79b0c59d309f2ebfc.tar.gz riscv-tests-ab4f35d0300e5dcfc62837d79b0c59d309f2ebfc.tar.bz2 | |
RV64 s{ll,ra,rl}w tests with non-canonical values
Diffstat (limited to 'isa/rv64ui/srlw.S')
| -rw-r--r-- | isa/rv64ui/srlw.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/isa/rv64ui/srlw.S b/isa/rv64ui/srlw.S index 24a492a..f0d1dae 100644 --- a/isa/rv64ui/srlw.S +++ b/isa/rv64ui/srlw.S @@ -43,6 +43,13 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee ); TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 ); + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- |