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| author | Andrew Waterman <andrew@sifive.com> | 2017-08-04 00:23:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-08-04 00:24:37 -0700 |
| commit | 7ab7ad44e66ba9bc2d91e04773efa4f87a1d8a3b (patch) | |
| tree | a812037174bae4e6667edd66ef9be5074b7d1855 /isa/rv64uc | |
| parent | ea9e37ff1411a8648710b5539b0971bb5ae9571f (diff) | |
| download | riscv-tests-7ab7ad44e66ba9bc2d91e04773efa4f87a1d8a3b.zip riscv-tests-7ab7ad44e66ba9bc2d91e04773efa4f87a1d8a3b.tar.gz riscv-tests-7ab7ad44e66ba9bc2d91e04773efa4f87a1d8a3b.tar.bz2 | |
Improve RVC test
Make the page-crossing instruction non-idempotent to detect erroneously
executing the first 16 bits of the instruction with garbage MSBs.
Diffstat (limited to 'isa/rv64uc')
| -rw-r--r-- | isa/rv64uc/rvc.S | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S index 2b8acd2..b0766a9 100644 --- a/isa/rv64uc/rvc.S +++ b/isa/rv64uc/rvc.S @@ -22,8 +22,7 @@ RVTEST_CODE_BEGIN // Make sure fetching a 4-byte instruction across a page boundary works. li TESTNUM, 2 li a1, 666 - li a2, 1 - RVC_TEST_CASE (2, a1, 2, \ + TEST_CASE (2, a1, 667, \ j 1f; \ .align 3; \ data: \ @@ -31,7 +30,7 @@ RVTEST_CODE_BEGIN .dword 0xfedcba9876543210; \ .align 12; \ .skip 4094; \ - 1: addi a1, a2, 1) + 1: addi a1, a1, 1) li sp, 0x1234 RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020) |