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| author | Andrew Waterman <andrew@sifive.com> | 2016-11-21 15:29:09 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2016-11-21 15:29:09 -0800 |
| commit | b68b39031a730ecc155ed87fba2ed5f111d0ab07 (patch) | |
| tree | 0bee833b8998b094b1b4ed18087538a5d1ae515e /isa/rv64ua/amoswap_d.S | |
| parent | e135e91b72ea79df1d023262d772cbc4759a4738 (diff) | |
| download | riscv-tests-b68b39031a730ecc155ed87fba2ed5f111d0ab07.zip riscv-tests-b68b39031a730ecc155ed87fba2ed5f111d0ab07.tar.gz riscv-tests-b68b39031a730ecc155ed87fba2ed5f111d0ab07.tar.bz2 | |
Remove cache miss test from all but one AMO test
This doesn't reduce coverage for cache-based RV64 systems, but will
improve test runtime and work around the need for smaller test footprint
for scratchpad-based RV32 systems.
I would argue that these microarchitectural tests should be in the
domain of torture, and that the last one should be removed, too.
Diffstat (limited to 'isa/rv64ua/amoswap_d.S')
| -rw-r--r-- | isa/rv64ua/amoswap_d.S | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/isa/rv64ua/amoswap_d.S b/isa/rv64ua/amoswap_d.S index 628f537..6b07d74 100644 --- a/isa/rv64ua/amoswap_d.S +++ b/isa/rv64ua/amoswap_d.S @@ -18,13 +18,6 @@ RVTEST_CODE_BEGIN li a1, 0xfffffffffffff800; \ la a3, amo_operand; \ sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ amoswap.d a4, a1, 0(a3); \ ) @@ -33,15 +26,6 @@ RVTEST_CODE_BEGIN # try again after a cache miss TEST_CASE(4, a4, 0xfffffffffffff800, \ li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ amoswap.d a4, a1, 0(a3); \ ) @@ -62,4 +46,3 @@ RVTEST_DATA_END .align 3 amo_operand: .dword 0 - .skip 65536 |