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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-17 04:35:24 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-17 04:59:31 -0700 |
| commit | f84936393dccd1367d3cb2a1fa060e77eb7babec (patch) | |
| tree | 843e9307309a1ef9a9df916915137b68b83508b3 /isa/rv64sv | |
| parent | 211d78276b07b17f831cefaf79961d3e6dad3c90 (diff) | |
| download | riscv-tests-f84936393dccd1367d3cb2a1fa060e77eb7babec.zip riscv-tests-f84936393dccd1367d3cb2a1fa060e77eb7babec.tar.gz riscv-tests-f84936393dccd1367d3cb2a1fa060e77eb7babec.tar.bz2 | |
relay hwacha cause/aux to scause/sbadaddr
Diffstat (limited to 'isa/rv64sv')
| -rw-r--r-- | isa/rv64sv/illegal_cfg_nfpr.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_cfg_nxpr.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_inst.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_vt_inst.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/ma_utld.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/ma_utsd.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vld.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vsd.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vt_inst.S | 4 | ||||
| -rw-r--r-- | isa/rv64sv/privileged_inst.S | 4 |
10 files changed, 20 insertions, 20 deletions
diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S index a2c9827..03227eb 100644 --- a/isa/rv64sv/illegal_cfg_nfpr.S +++ b/isa/rv64sv/illegal_cfg_nfpr.S @@ -30,12 +30,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_ILLEGAL_CFG bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr li a4, 1 bne a3,a4,fail diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S index db07744..dc4d3a4 100644 --- a/isa/rv64sv/illegal_cfg_nxpr.S +++ b/isa/rv64sv/illegal_cfg_nxpr.S @@ -29,12 +29,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_ILLEGAL_CFG bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr li a4, 0 bne a3,a4,fail diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S index ae46fe0..b7dfc28 100644 --- a/isa/rv64sv/illegal_inst.S +++ b/isa/rv64sv/illegal_inst.S @@ -36,12 +36,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr li a4, 0xff00002b bne a3,a4,fail diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S index dd61697..e216413 100644 --- a/isa/rv64sv/illegal_vt_inst.S +++ b/isa/rv64sv/illegal_vt_inst.S @@ -44,12 +44,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION bne a3,a4,fail # check badvaddr - vxcptaux a3 + csrr a3, sbadaddr la a4,illegal bne a3,a4,fail diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S index 398396e..79b21b1 100644 --- a/isa/rv64sv/ma_utld.S +++ b/isa/rv64sv/ma_utld.S @@ -40,12 +40,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_MISALIGNED_LOAD bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr la a4,dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S index 1390b54..9bd3cd8 100644 --- a/isa/rv64sv/ma_utsd.S +++ b/isa/rv64sv/ma_utsd.S @@ -42,12 +42,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_MISALIGNED_STORE bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr la a4, dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S index 4276b64..85882b8 100644 --- a/isa/rv64sv/ma_vld.S +++ b/isa/rv64sv/ma_vld.S @@ -41,12 +41,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_MISALIGNED_LOAD bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr la a4,dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S index 2271e8f..35cb828 100644 --- a/isa/rv64sv/ma_vsd.S +++ b/isa/rv64sv/ma_vsd.S @@ -44,12 +44,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_MISALIGNED_STORE bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr la a4,dest+1 bne a3,a4,fail diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S index 25c23c5..d7c96b3 100644 --- a/isa/rv64sv/ma_vt_inst.S +++ b/isa/rv64sv/ma_vt_inst.S @@ -34,12 +34,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH bne a3,a4,fail # check badvaddr - vxcptaux a3 + csrr a3, sbadaddr la a4,vtcode1+2 andi a3, a3, -4 # mask off lower bits so that may andi a4, a4, -4 # ignore impl. specific behavior diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S index b7b169e..65c5288 100644 --- a/isa/rv64sv/privileged_inst.S +++ b/isa/rv64sv/privileged_inst.S @@ -36,12 +36,12 @@ handler: li TESTNUM,2 # check cause - vxcptcause a3 + csrr a3, scause li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION bne a3,a4,fail # check vec irq aux - vxcptaux a3 + csrr a3, sbadaddr la a4, privileged_inst lw a5, 0(a4) bne a3,a5,fail |