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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-20 23:38:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-20 23:39:33 -0700 |
| commit | 7155726ad6612a7f87318d84ac496672f9bbc8ce (patch) | |
| tree | 41536c613ff20382b4a9a789e91e11a176c027d5 /isa/rv64sv/ma_vt_inst.S | |
| parent | f66d9faeca28d491115eb60a8f5b6b747f255a09 (diff) | |
| download | riscv-tests-7155726ad6612a7f87318d84ac496672f9bbc8ce.zip riscv-tests-7155726ad6612a7f87318d84ac496672f9bbc8ce.tar.gz riscv-tests-7155726ad6612a7f87318d84ac496672f9bbc8ce.tar.bz2 | |
Remove Hwacha v3 tests
Diffstat (limited to 'isa/rv64sv/ma_vt_inst.S')
| -rw-r--r-- | isa/rv64sv/ma_vt_inst.S | 99 |
1 files changed, 0 insertions, 99 deletions
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S deleted file mode 100644 index a257942..0000000 --- a/isa/rv64sv/ma_vt_inst.S +++ /dev/null @@ -1,99 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ma_vt_inst.S -#----------------------------------------------------------------------------- -# -# Test misaligned vt instruction trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - lui a0,%hi(vtcode1+2) - vf %lo(vtcode1+2)(a0) -1: j 1b - -vtcode1: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH - bne a3,a4,fail - - # check badvaddr - csrr a3, sbadaddr - la a4,vtcode1+2 - andi a3, a3, -4 # mask off lower bits so that may - andi a4, a4, -4 # ignore impl. specific behavior - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END |