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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-16 02:10:17 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-16 02:10:17 -0700 |
| commit | dd0d4036430dc812c9168fad8870d58ce151f498 (patch) | |
| tree | 1e72637f1c2742de6a0e9bd6bd049d0215ce9b66 /isa/rv64sv/ma_utld.S | |
| parent | 62f8f78b5fc18e2f89e4b6429352ca4c980908c7 (diff) | |
| download | riscv-tests-dd0d4036430dc812c9168fad8870d58ce151f498.zip riscv-tests-dd0d4036430dc812c9168fad8870d58ce151f498.tar.gz riscv-tests-dd0d4036430dc812c9168fad8870d58ce151f498.tar.bz2 | |
revamp vector tests with new privileged spec, and add scalar pt tests
Diffstat (limited to 'isa/rv64sv/ma_utld.S')
| -rw-r--r-- | isa/rv64sv/ma_utld.S | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S index 3bd7437..398396e 100644 --- a/isa/rv64sv/ma_utld.S +++ b/isa/rv64sv/ma_utld.S @@ -10,20 +10,11 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV64S +RVTEST_RV64SV RVTEST_CODE_BEGIN - li a0, SR_EA | SR_EI - csrs status, a0 - la a3,handler - csrw evec,a3 # set exception handler - - csrr a3,status - li a4,(1 << IRQ_COP) - slli a4,a4,SR_IM_SHIFT - or a3,a3,a4 # enable IM[COP] - csrw status,a3 + csrw stvec,a3 # set exception handler vsetcfg 32,0 li a3,4 |