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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-24 14:33:35 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-24 14:33:48 -0800 |
| commit | 2e4376c4acf1e9460ca714102dd955a9bd10c488 (patch) | |
| tree | 9bf77f937059b71c7d51316f92f1cff29b872d5f /isa/rv64sv/ma_utld.S | |
| parent | fdf5e6f97d53722d7ec44c4591f1ab740a092808 (diff) | |
| download | riscv-tests-2e4376c4acf1e9460ca714102dd955a9bd10c488.zip riscv-tests-2e4376c4acf1e9460ca714102dd955a9bd10c488.tar.gz riscv-tests-2e4376c4acf1e9460ca714102dd955a9bd10c488.tar.bz2 | |
Update to new privileged ISA
Diffstat (limited to 'isa/rv64sv/ma_utld.S')
| -rw-r--r-- | isa/rv64sv/ma_utld.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S index aff6e1a..c48e134 100644 --- a/isa/rv64sv/ma_utld.S +++ b/isa/rv64sv/ma_utld.S @@ -11,17 +11,17 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - setpcr status, SR_EA # enable accelerator - setpcr status, SR_EI # enable interrupt + li a0, SR_EA | SR_EI + csrs status, a0 la a3,handler - mtpcr a3,evec # set exception handler + csrw evec,a3 # set exception handler - mfpcr a3,status + csrr a3,status li a4,(1 << IRQ_COP) slli a4,a4,SR_IM_SHIFT or a3,a3,a4 # enable IM[COP] - mtpcr a3,status + csrw status,a3 vsetcfg 32,0 li a3,4 |