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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-11-01 00:34:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-11-01 00:35:17 -0700 |
| commit | f7bb852141c107722bdb0302d11b6f992a6991d5 (patch) | |
| tree | 9dd5c2beea6bae9a7e0ca522b7c403afe5fea155 /isa/rv64si | |
| parent | ce405b436277a52f764aa15551603e6dce3f568f (diff) | |
| download | riscv-tests-f7bb852141c107722bdb0302d11b6f992a6991d5.zip riscv-tests-f7bb852141c107722bdb0302d11b6f992a6991d5.tar.gz riscv-tests-f7bb852141c107722bdb0302d11b6f992a6991d5.tar.bz2 | |
Make sure FP stores don't write memory if mstatus.FS=0.
Diffstat (limited to 'isa/rv64si')
| -rw-r--r-- | isa/rv64si/csr.S | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 1f7bb77..13dbf26 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -35,6 +35,19 @@ RVTEST_CODE_BEGIN TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch); #ifdef __MACHINE_MODE + # Is F extension present? + csrr a0, misa + andi a0, a0, (1 << ('F' - 'A')) + beqz a0, 1f + # If so, make sure FP stores have no effect when mstatus.FS is off. + li a1, MSTATUS_FS + csrs mstatus, a1 + fmv.s.x f0, x0 + csrc mstatus, a1 + la a1, fsw_data + TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1)); +1: + # Figure out if 'U' is set in misa csrr a0, misa # a0 = csr(misa) srli a0, a0, 20 # a0 = a0 >> 20 @@ -53,15 +66,15 @@ RVTEST_CODE_BEGIN # Make sure writing the cycle counter causes an exception. # Don't run in supervisor, as we don't delegate illegal instruction traps. #ifdef __MACHINE_MODE - TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0); + TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0); #endif # Make sure reading status in user mode causes an exception. # Don't run in supervisor, as we don't delegate illegal instruction traps. #ifdef __MACHINE_MODE - TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus) + TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus) #else - TEST_CASE(11, x0, 0, nop) + TEST_CASE(12, x0, 0, nop) #endif finish: @@ -72,12 +85,13 @@ finish: .align 2 stvec_handler: - # Trapping on tests 10 and 11 is good news. + # Trapping on tests 10-12 is good news. # Note that since the test didn't complete, TESTNUM is smaller by 1. li t0, 9 - beq TESTNUM, t0, privileged - li t0, 10 - beq TESTNUM, t0, privileged + bltu TESTNUM, t0, 1f + li t0, 11 + bleu TESTNUM, t0, privileged +1: # catch RVTEST_PASS and kick it up to M-mode csrr t0, scause @@ -101,6 +115,6 @@ RVTEST_CODE_END .data RVTEST_DATA_BEGIN - TEST_DATA +fsw_data: .word 1 RVTEST_DATA_END |