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| author | SLAMET RIANTO <59614506+slametr-sifive@users.noreply.github.com> | 2021-05-10 17:25:00 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-10 15:25:00 -0700 |
| commit | c22b105d5a333cce3b2bef1ef3a0d2b773a54dd5 (patch) | |
| tree | 809d44201edffc009fa344c4827f968935e1c77e /isa/rv64si | |
| parent | c9f43c1652c1d8abf85f3466f41ffd5ec4d911d6 (diff) | |
| download | riscv-tests-c22b105d5a333cce3b2bef1ef3a0d2b773a54dd5.zip riscv-tests-c22b105d5a333cce3b2bef1ef3a0d2b773a54dd5.tar.gz riscv-tests-c22b105d5a333cce3b2bef1ef3a0d2b773a54dd5.tar.bz2 | |
Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support CLIC mode. (#336)
illegal.S:
- After the test enters supervisor mode, check if paging is supported.
- If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following:
-- SFENCE.VMA causing illegal instruction trap regardless of TVM.
-- Access to SATP does not trap.
-- Jump to the same TSR check as regular S-mode
-- End test
sbreak.S & scall.S:
- Before checking for scause, check if the core is in CLIC-mode (mtvec[1]).
- If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value.
- Otherwise, don't mask off any scause bits as in the original test.
Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
Diffstat (limited to 'isa/rv64si')
| -rw-r--r-- | isa/rv64si/sbreak.S | 7 | ||||
| -rw-r--r-- | isa/rv64si/scall.S | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S index 31efff8..8de8e15 100644 --- a/isa/rv64si/sbreak.S +++ b/isa/rv64si/sbreak.S @@ -35,6 +35,13 @@ do_break: stvec_handler: li t1, CAUSE_BREAKPOINT csrr t0, scause + # Check if CLIC mode + csrr t2, stvec + andi t2, t2, 2 + # Skip masking if non-CLIC mode + beqz t2, skip_mask + andi t0, t0, 255 +skip_mask: bne t0, t1, fail la t1, do_break csrr t0, sepc diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S index 9956e03..5dda6bb 100644 --- a/isa/rv64si/scall.S +++ b/isa/rv64si/scall.S @@ -67,6 +67,13 @@ do_scall: .global stvec_handler stvec_handler: csrr t0, scause + # Check if CLIC mode + csrr t2, stvec + andi t2, t2, 2 + # Skip masking if non-CLIC mode + beqz t2, skip_mask + andi t0, t0, 255 +skip_mask: bne t0, t1, fail la t2, do_scall csrr t0, sepc |