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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-25 16:25:42 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-25 16:25:42 -0700 |
commit | 9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc (patch) | |
tree | 7e1db6f26a9d315cf164154a43623a33daf835a6 /isa/rv64si | |
parent | a398a9baeccebbf7b8c7bd04edaac5e0d02cd7bf (diff) | |
download | riscv-tests-9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc.zip riscv-tests-9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc.tar.gz riscv-tests-9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc.tar.bz2 |
split out S-mode tests and M-mode tests
Diffstat (limited to 'isa/rv64si')
-rw-r--r-- | isa/rv64si/Makefrag | 7 | ||||
-rw-r--r-- | isa/rv64si/csr.S | 21 | ||||
-rw-r--r-- | isa/rv64si/dirty.S | 84 | ||||
-rw-r--r-- | isa/rv64si/illegal.S | 11 | ||||
-rw-r--r-- | isa/rv64si/ipi.S | 62 | ||||
-rw-r--r-- | isa/rv64si/ma_addr.S | 25 | ||||
-rw-r--r-- | isa/rv64si/ma_fetch.S | 11 | ||||
-rw-r--r-- | isa/rv64si/sbreak.S | 11 | ||||
-rw-r--r-- | isa/rv64si/scall.S | 11 | ||||
-rw-r--r-- | isa/rv64si/timer.S | 39 |
10 files changed, 96 insertions, 186 deletions
diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag index 802fc55..f19d840 100644 --- a/isa/rv64si/Makefrag +++ b/isa/rv64si/Makefrag @@ -10,12 +10,7 @@ rv64si_sc_tests = \ scall \ sbreak \ timer \ - dirty \ - -rv64si_mc_tests = \ - ipi \ rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) -rv64si_pm_tests = $(addprefix rv64si-pm-, $(rv64si_mc_tests)) -spike_tests += $(rv64si_p_tests) $(rv64si_pm_tests) +spike_tests += $(rv64si_p_tests) diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index edaaeb3..5d4b309 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -13,9 +13,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - # Set up stvec in case we trap. - la t0, stvec - csrw stvec, t0 +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define stvec_handler mtvec_handler + #undef SSTATUS_PS + #define SSTATUS_PS MSTATUS_PRV1 +#endif + csrwi scycle, 0 csrwi sscratch, 3 @@ -31,7 +38,7 @@ RVTEST_CODE_BEGIN # Make sure writing the cycle counter causes an exception. TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0); - # Enter user mode + # jump to user land li t0, SSTATUS_PS csrc sstatus, t0 la t0, 1f @@ -51,7 +58,7 @@ RVTEST_CODE_BEGIN # We should only fall through to this if scall failed. TEST_PASSFAIL -stvec: +stvec_handler: # Trapping on tests 10, 11, and 13 is usually good news. # Note that since the test didn't complete, TESTNUM is smaller by 1. li t0, 9 @@ -65,7 +72,7 @@ stvec: j fail privileged: - # Make sure CAUSE indicates a lack of privilege. + # Make sure scause indicates a lack of privilege. csrr t0, scause li t1, CAUSE_ILLEGAL_INSTRUCTION bne t0, t1, fail @@ -76,7 +83,7 @@ privileged: sret syscall: - # Make sure CAUSE indicates a syscall. + # Make sure scause indicates a syscall. csrr t0, scause li t1, CAUSE_ECALL bne t0, t1, fail diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S deleted file mode 100644 index e5f4db6..0000000 --- a/isa/rv64si/dirty.S +++ /dev/null @@ -1,84 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# dirty.S -#----------------------------------------------------------------------------- -# -# Test VM referenced and dirty bits. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64M -RVTEST_CODE_BEGIN - - # Turn on VM with superpage identity mapping - la a1, handler - csrw stvec, a1 - la a1, page_table_1 - csrw sptbr, a1 - sfence.vm - li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV43) | ((MSTATUS_PRV1 & ~(MSTATUS_PRV1<<1)) * PRV_S) - csrs mstatus, a1 - la a1, 1f - csrw mepc, a1 - eret -1: - - # Try a faulting store to make sure dirty bit is not set - li TESTNUM, 2 - li t0, 1 - sd t0, dummy, t1 - - # Load new page table - li TESTNUM, 3 - la t0, page_table_2 - csrw sptbr, t0 - sfence.vm - - # Try a non-faulting store to make sure dirty bit is set - sd t0, dummy, t1 - - # Make sure R and D bits are set - lw t0, page_table_2 - li t1, PTE_R | PTE_D - and t0, t0, t1 - bne t0, t1, die - - RVTEST_PASS - - TEST_PASSFAIL - -handler: - csrr t0, scause - li t1, 2 - bne TESTNUM, t1, 1f - # Make sure R bit is set - lw t0, page_table_1 - li t1, PTE_R - and t0, t0, t1 - bne t0, t1, die - - # Make sure D bit is clear - lw t0, page_table_1 - li t1, PTE_D - and t0, t0, t1 - beq t0, t1, die - - csrr t0, sepc - add t0, t0, 4 - csrw sepc, t0 - sret - -die: - RVTEST_FAIL - -.data -.align 13 -page_table_1: .dword PTE_V | PTE_SX | PTE_SR -dummy: .dword 0 -.align 13 -page_table_2: .dword PTE_V | PTE_SX | PTE_SR | PTE_SW - -RVTEST_CODE_END diff --git a/isa/rv64si/illegal.S b/isa/rv64si/illegal.S index b068118..43068b4 100644 --- a/isa/rv64si/illegal.S +++ b/isa/rv64si/illegal.S @@ -13,8 +13,13 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - la t0, stvec - csrw stvec, t0 +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define stvec_handler mtvec_handler +#endif li TESTNUM, 2 .word 0 @@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL -stvec: +stvec_handler: li t1, CAUSE_ILLEGAL_INSTRUCTION csrr t0, scause bne t0, t1, fail diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S deleted file mode 100644 index e45c663..0000000 --- a/isa/rv64si/ipi.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ipi.S -#----------------------------------------------------------------------------- -# -# Test interprocessor interrupts. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64M -RVTEST_CODE_BEGIN - - # enable interrupts - csrs mstatus, MSTATUS_IE - - # get a unique core id - la a0, coreid - li a1, 1 - amoadd.w a2, a1, (a0) - - # for now, only run this on core 0 - 1:li a3, 1 - bgeu a2, a3, 1b - - # wait for all cores to boot - 1: lw a1, (a0) - bltu a1, a3, 1b - - # IPI dominoes - csrr a0, hartid - 1: bnez a0, 1b - add a0, a0, 1 - rem a0, a0, a3 - csrw send_ipi, a0 - 1: j 1b - -mtvec: - csrr a0, hartid - bnez a0, 2f - RVTEST_PASS - - TEST_PASSFAIL - - 2: add a0, a0, 1 - rem a0, a0, a3 - csrw send_ipi, a0 - 1: j 1b - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -coreid: .word 0 -foo: .word 0 - -RVTEST_DATA_END diff --git a/isa/rv64si/ma_addr.S b/isa/rv64si/ma_addr.S index 19abe96..525e028 100644 --- a/isa/rv64si/ma_addr.S +++ b/isa/rv64si/ma_addr.S @@ -13,10 +13,18 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - la s0, stvec_load +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define stvec_handler mtvec_handler +#endif + + la s0, stvec_handler - la t0, stvec_load - csrw stvec, t0 + # indicate it's a load test + li s1, 0 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \ li TESTNUM, testnum; \ @@ -43,8 +51,8 @@ RVTEST_CODE_BEGIN MISALIGNED_LDST_TEST(16, ld, s0, 7) #endif - la t0, stvec_store - csrw stvec, t0 + # indicate it's a store test + li s1, 1 MISALIGNED_LDST_TEST(22, sh, s0, 1) MISALIGNED_LDST_TEST(23, sw, s0, 1) @@ -64,7 +72,10 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL .align 3 -stvec_load: +stvec_handler: + bnez s1, test_store + +test_load: li t1, CAUSE_MISALIGNED_LOAD csrr t0, scause bne t0, t1, fail @@ -73,7 +84,7 @@ stvec_load: csrw sepc, t0 sret -stvec_store: +test_store: li t1, CAUSE_MISALIGNED_STORE csrr t0, scause bne t0, t1, fail diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index ae8377d..272a9eb 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -13,8 +13,13 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - la t0, stvec - csrw stvec, t0 +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define stvec_handler mtvec_handler +#endif #ifndef __rvc li TESTNUM, 2 @@ -47,7 +52,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL -stvec: +stvec_handler: # tests 2 and 4 should trap li a0, 2 beq TESTNUM, a0, 1f diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S index dbdf7ae..bf38434 100644 --- a/isa/rv64si/sbreak.S +++ b/isa/rv64si/sbreak.S @@ -13,8 +13,13 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - la t0, stvec - csrw stvec, t0 +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define stvec_handler mtvec_handler +#endif li TESTNUM, 2 sbreak @@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL -stvec: +stvec_handler: li t1, CAUSE_BREAKPOINT csrr t0, scause bne t0, t1, fail diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S index aa543e9..e1c13b6 100644 --- a/isa/rv64si/scall.S +++ b/isa/rv64si/scall.S @@ -13,8 +13,13 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - la t0, stvec - csrw stvec, t0 +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define stvec_handler mtvec_handler +#endif li TESTNUM, 2 scall @@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL -stvec: +stvec_handler: li t1, CAUSE_ECALL csrr t0, scause bne t0, t1, fail diff --git a/isa/rv64si/timer.S b/isa/rv64si/timer.S index 584ced7..c78d922 100644 --- a/isa/rv64si/timer.S +++ b/isa/rv64si/timer.S @@ -1,10 +1,10 @@ # See LICENSE for license details. #***************************************************************************** -# ipi.S +# timer.S #----------------------------------------------------------------------------- # -# Test interprocessor interrupts. +# Test timer interrupts. # #include "riscv_test.h" @@ -13,16 +13,35 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - # clear pending IPIs then enable interrupts +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define stvec_handler mtvec_handler + #undef SSTATUS_PS + #define SSTATUS_PS MSTATUS_PRV1 + #undef SSTATUS_IE + #define SSTATUS_IE MSTATUS_IE + #undef SSTATUS_TIE + #define SSTATUS_TIE MSTATUS_STIE +#endif + li s8, 0 # number of taken timer interrupts li s9, 10 # how many interrupts to run for - la a0, handler - csrw stvec, a0 csrw stimecmp, 1 csrw stime, 0 li a0, SSTATUS_IE | SSTATUS_TIE csrs sstatus, a0 + # jump to user land + li t0, SSTATUS_PS + csrc sstatus, t0 + la t0, 1f + csrw sepc, t0 + sret + 1: + # advance an LFSR 1000 times li s0, 1023 li s4, 0 @@ -36,8 +55,6 @@ RVTEST_CODE_BEGIN add s4, s4, 1 bltu s8, s9, 1b - csrc sstatus, SSTATUS_IE - # make sure the LFSR was computed correctly li s1, 1023 remu s4, s4, s1 @@ -52,7 +69,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL -handler: +stvec_handler: li TESTNUM, 3 csrr t0, scause bgez t0, fail @@ -66,7 +83,13 @@ handler: csrw stimecmp, t0 add s8, s8, 1 + bltu s8, s9, stvec_return + + li t0, SSTATUS_PS + csrs sstatus, t0 + csrc sstatus, SSTATUS_IE +stvec_return: sret .data |