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| author | Christopher Celio <celio@eecs.berkeley.edu> | 2014-08-28 03:52:17 -0700 |
|---|---|---|
| committer | Christopher Celio <celio@eecs.berkeley.edu> | 2014-08-28 03:52:17 -0700 |
| commit | 3af71c779ae5f34c16c1133b972b99ee9c2338b5 (patch) | |
| tree | 0379cdff8c046bd46d86e8e69ad2017b6049b188 /isa/rv32ui/simple.S | |
| parent | b6bcab870b1eaf0ed7b75e5458f9880510d26100 (diff) | |
| download | riscv-tests-3af71c779ae5f34c16c1133b972b99ee9c2338b5.zip riscv-tests-3af71c779ae5f34c16c1133b972b99ee9c2338b5.tar.gz riscv-tests-3af71c779ae5f34c16c1133b972b99ee9c2338b5.tar.bz2 | |
Added "simple" test to rv32ui.
Diffstat (limited to 'isa/rv32ui/simple.S')
| -rw-r--r-- | isa/rv32ui/simple.S | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/isa/rv32ui/simple.S b/isa/rv32ui/simple.S new file mode 100644 index 0000000..c247ce0 --- /dev/null +++ b/isa/rv32ui/simple.S @@ -0,0 +1,25 @@ +#***************************************************************************** +# simple.S +#----------------------------------------------------------------------------- +# +# This is the most basic self checking test. If your simulator does not +# pass thiss then there is little chance that it will pass any of the +# more complicated self checking tests. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + +RVTEST_PASS + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |