Rv32ud tests (#108)

* Probably implemented the changes required to support fadd test for rv32ud

* Created test files in rv32ud, implemented working(?) test for ldst

* fclass, fcvt_w, fmin and recoding seem to be working now

* Got fdiv (and sqrt) tests working

* fmadd tests seem to work

* fcmp works

* [WIP] fcvt working, but lacks a 32-bit implementation of the final test

* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST

* Added Makefrag for rv32ud tests and included in main isa Makefile

* Don't run 64-bit tests if the defined XLEN is 32

12 files changed, 127 insertions, 0 deletions

diff --git a/isa/rv32ud/Makefrag b/isa/rv32ud/Makefrag
new file mode 100644
index 0000000..998078d
--- /dev/null
+++ b/isa/rv32ud/Makefrag
@@ -0,0 +1,15 @@
+#=======================================================================
+# Makefrag for rv32ud tests
+#-----------------------------------------------------------------------
+
+rv32ud_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst recoding \
+
+# TODO: use this line instead of the last of the previous once move and structural tests have been implemented
+#        ldst move structural recoding \
+
+rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests))
+rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests))
+
+spike32_tests += $(rv32ud_p_tests) $(rv32ud_v_tests)
diff --git a/isa/rv32ud/fadd.S b/isa/rv32ud/fadd.S
new file mode 100644
index 0000000..5fb9090
--- /dev/null
+++ b/isa/rv32ud/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fadd.S"
diff --git a/isa/rv32ud/fclass.S b/isa/rv32ud/fclass.S
new file mode 100644
index 0000000..c960ad6
--- /dev/null
+++ b/isa/rv32ud/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fclass.S"
diff --git a/isa/rv32ud/fcmp.S b/isa/rv32ud/fcmp.S
new file mode 100644
index 0000000..55d1c3a
--- /dev/null
+++ b/isa/rv32ud/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fcmp.S"
diff --git a/isa/rv32ud/fcvt.S b/isa/rv32ud/fcvt.S
new file mode 100644
index 0000000..8811b6e
--- /dev/null
+++ b/isa/rv32ud/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fcvt.S"
diff --git a/isa/rv32ud/fcvt_w.S b/isa/rv32ud/fcvt_w.S
new file mode 100644
index 0000000..3447530
--- /dev/null
+++ b/isa/rv32ud/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt_w.S"
diff --git a/isa/rv32ud/fdiv.S b/isa/rv32ud/fdiv.S
new file mode 100644
index 0000000..793e51a
--- /dev/null
+++ b/isa/rv32ud/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fdiv.S"
diff --git a/isa/rv32ud/fmadd.S b/isa/rv32ud/fmadd.S
new file mode 100644
index 0000000..e60934c
--- /dev/null
+++ b/isa/rv32ud/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fmadd.S"
diff --git a/isa/rv32ud/fmin.S b/isa/rv32ud/fmin.S
new file mode 100644
index 0000000..c80c880
--- /dev/null
+++ b/isa/rv32ud/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fmin.S"
diff --git a/isa/rv32ud/ldst.S b/isa/rv32ud/ldst.S
new file mode 100644
index 0000000..e39fe30
--- /dev/null
+++ b/isa/rv32ud/ldst.S
@@ -0,0 +1,42 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+  la s0, tdat
+  TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/isa/rv32ud/move.S b/isa/rv32ud/move.S
new file mode 100644
index 0000000..4551ffd
--- /dev/null
+++ b/isa/rv32ud/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/move.S"
diff --git a/isa/rv32ud/recoding.S b/isa/rv32ud/recoding.S
new file mode 100644
index 0000000..5dc0113
--- /dev/null
+++ b/isa/rv32ud/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/recoding.S"