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authorPalmer Dabbelt <palmer@dabbelt.com>2016-07-12 09:19:08 -0700
committerPalmer Dabbelt <palmer@dabbelt.com>2016-07-12 09:19:08 -0700
commit00df2be7a414d34c7633142c73ac6130f6cbbd4b (patch)
tree49ade5408f077f851fd90280fc300709148883f9 /isa/rv32ua/amoswap_w.S
parentd82a880f81cb5d197f712bbd17e821e0d70d7b75 (diff)
parent3dc00e7b04834f862a074ac8822892e1ecfc009c (diff)
downloadriscv-tests-smi-demo.zip
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Merge commit '3dc00e7' into smi-demosmi-demo
Diffstat (limited to 'isa/rv32ua/amoswap_w.S')
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diff --git a/isa/rv32ua/amoswap_w.S b/isa/rv32ua/amoswap_w.S
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+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffff800, \
+ li a1, 0x80000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536