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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-20 23:38:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-20 23:39:33 -0700 |
| commit | 7155726ad6612a7f87318d84ac496672f9bbc8ce (patch) | |
| tree | 41536c613ff20382b4a9a789e91e11a176c027d5 /isa/macros/scalar | |
| parent | f66d9faeca28d491115eb60a8f5b6b747f255a09 (diff) | |
| download | riscv-tests-7155726ad6612a7f87318d84ac496672f9bbc8ce.zip riscv-tests-7155726ad6612a7f87318d84ac496672f9bbc8ce.tar.gz riscv-tests-7155726ad6612a7f87318d84ac496672f9bbc8ce.tar.bz2 | |
Remove Hwacha v3 tests
Diffstat (limited to 'isa/macros/scalar')
| -rw-r--r-- | isa/macros/scalar/test_macros.h | 123 |
1 files changed, 0 insertions, 123 deletions
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 6242f0b..48ce028 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -564,129 +564,6 @@ test_ ## testnum: \ .double result; \ 1: - -#----------------------------------------------------------------------- -# RV64SV MACROS -#----------------------------------------------------------------------- - -#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \ - la a0, handler ## testnum; \ - csrw stvec, a0; \ - vsetcfg nxreg, nfreg; \ - li a0, 4; \ - vsetvl a0, a0; \ - la a0, src1; \ - la a1, src2; \ - vld vx2, a0; \ - vld vx3, a1; \ - lui a0,%hi(vtcode1 ## testnum); \ - vf %lo(vtcode1 ## testnum)(a0); \ - la reg2, dest; \ -illegal ## testnum: \ - inst reg1, reg2; \ - la a3, dest; \ - vsd vx2, a3; \ - fence; \ -vtcode1 ## testnum: \ - add x2, x2, x3; \ - stop; \ -vtcode2 ## testnum: \ - add x2, x2, x3; \ - stop; \ -handler ## testnum: \ - vxcptkill; \ - li TESTNUM,2; \ - csrr a0, scause; \ - li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \ - bne a0,a1,fail; \ - csrr a0, sbadaddr; \ - la a1, illegal ## testnum; \ - lw a2, 0(a1); \ - bne a0, a2, fail; \ - vsetcfg 32,0; \ - li a0,4; \ - vsetvl a0,a0; \ - la a0,src1; \ - la a1,src2; \ - vld vx2,a0; \ - vld vx3,a1; \ - lui a0,%hi(vtcode2 ## testnum); \ - vf %lo(vtcode2 ## testnum)(a0); \ - la a3,dest; \ - vsd vx2,a3; \ - fence; \ - ld a1,0(a3); \ - li a2,5; \ - li TESTNUM,2; \ - bne a1,a2,fail; \ - ld a1,8(a3); \ - li TESTNUM,3; \ - bne a1,a2,fail; \ - ld a1,16(a3); \ - li TESTNUM,4; \ - bne a1,a2,fail; \ - ld a1,24(a3); \ - li TESTNUM,5; \ - bne a1,a2,fail; \ - -#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ - la a0, handler ## testnum; \ - csrw stvec, a0; \ - vsetcfg nxreg, nfreg; \ - li a0, 4; \ - vsetvl a0, a0; \ - la a0, src1; \ - la a1, src2; \ - vld vx2, a0; \ - vld vx3, a1; \ - lui a0,%hi(vtcode1 ## testnum); \ - vf %lo(vtcode1 ## testnum)(a0); \ - la a3, dest; \ - vsd vx2, a3; \ - fence; \ -vtcode1 ## testnum: \ - add x2, x2, x3; \ -illegal ## testnum: \ - inst reg1, reg2, reg3; \ - stop; \ -vtcode2 ## testnum: \ - add x2, x2, x3; \ - stop; \ -handler ## testnum: \ - vxcptkill; \ - li TESTNUM,2; \ - csrr a0, scause; \ - li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \ - bne a0,a1,fail; \ - csrr a0, sbadaddr; \ - la a1,illegal ## testnum; \ - bne a0,a1,fail; \ - vsetcfg 32,0; \ - li a0,4; \ - vsetvl a0,a0; \ - la a0,src1; \ - la a1,src2; \ - vld vx2,a0; \ - vld vx3,a1; \ - lui a0,%hi(vtcode2 ## testnum); \ - vf %lo(vtcode2 ## testnum)(a0); \ - la a3,dest; \ - vsd vx2,a3; \ - fence; \ - ld a1,0(a3); \ - li a2,5; \ - li TESTNUM,2; \ - bne a1,a2,fail; \ - ld a1,8(a3); \ - li TESTNUM,3; \ - bne a1,a2,fail; \ - ld a1,16(a3); \ - li TESTNUM,4; \ - bne a1,a2,fail; \ - ld a1,24(a3); \ - li TESTNUM,5; \ - bne a1,a2,fail; \ - #----------------------------------------------------------------------- # Pass and fail code (assumes test num is in TESTNUM) #----------------------------------------------------------------------- |