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| author | Roger Chang <rogerycchang@google.com> | 2024-02-19 11:29:33 +0800 |
|---|---|---|
| committer | Roger Chang <rogerycchang@google.com> | 2024-02-19 11:29:33 +0800 |
| commit | a3498c6d2f770af95964a0a7ba46f285cecd1eb3 (patch) | |
| tree | 4d216b0e0c5f0989e052da725464c89d72ee873e /isa/Makefile | |
| parent | 45476161d6c42c321458027b70fc03a97f6e4ad7 (diff) | |
| download | riscv-tests-a3498c6d2f770af95964a0a7ba46f285cecd1eb3.zip riscv-tests-a3498c6d2f770af95964a0a7ba46f285cecd1eb3.tar.gz riscv-tests-a3498c6d2f770af95964a0a7ba46f285cecd1eb3.tar.bz2 | |
Add zbb test cases
Signed-off-by: Roger Chang <rogerycchang@google.com>
Diffstat (limited to 'isa/Makefile')
| -rw-r--r-- | isa/Makefile | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index ffd82ff..28ae6a6 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -15,6 +15,7 @@ include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64uzfh/Makefrag include $(src_dir)/rv64uzba/Makefrag +include $(src_dir)/rv64uzbb/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -28,6 +29,7 @@ include $(src_dir)/rv32uf/Makefrag include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfh/Makefrag include $(src_dir)/rv32uzba/Makefrag +include $(src_dir)/rv32uzbb/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -52,10 +54,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ define compile_template @@ -89,6 +91,7 @@ $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) $(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -100,6 +103,7 @@ $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) +$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) |