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| author | Nadime Barhoumi <nadime@riscv.org> | 2026-04-24 16:46:28 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-24 13:46:28 -0700 |
| commit | 0bbecd1a01c61a16ad45fdfd89f29ebfdb493d1d (patch) | |
| tree | 44c99b561b63858df13f11463a140352d22d695a /isa/Makefile | |
| parent | 933a897d8631773f385d45938facc466dddc7514 (diff) | |
| download | riscv-tests-master.tar.gz riscv-tests-master.tar.bz2 riscv-tests-master.zip | |
Adds four RV64 hypervisor tests exercising implicit G-stage faults raised
during VS-stage page table walks:
- 2-stage_translation_implicit_load_error
- 2-stage_translation_implicit_load_error_hs
- 2-stage_translation_implicit_store_error
- 2-stage_translation_implicit_store_error_hs
The load variants trigger the fault by leaving the G-stage PTE invalid
(no PTE_V), causing the implicit PTE read during the VS-stage walk to
fault. The store variants omit PTE_W on the G-stage PTE, so G-stage
grants read but denies write, causing the implicit PTE store for the
A/D writeback to fail. These require hardware A/D updates, which occur
when Svadu is enabled via ADUE.
Each test checks mcause/scause, mtval/stval, and mtval2/htval and
verifies that mtinst/htinst contains the expected pseudoinstruction:
- 0x3000 — 64-bit implicit VS-stage PTE load
- 0x3020 — 64-bit implicit VS-stage PTE store
Diffstat (limited to 'isa/Makefile')
| -rw-r--r-- | isa/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/isa/Makefile b/isa/Makefile index 0f0106f..d5e67cd 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -26,6 +26,7 @@ include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag include $(src_dir)/rv64mzicbo/Makefrag include $(src_dir)/hypervisor/Makefrag +include $(src_dir)/hypervisor-svadu/Makefrag else include $(src_dir)/rv32ui/Makefrag include $(src_dir)/rv32uc/Makefrag @@ -123,6 +124,7 @@ $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64d)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64d)) $(eval $(call compile_template,rv64mi,-march=rv64g -mabi=lp64d)) $(eval $(call compile_template,hypervisor,-march=rv64gh -mabi=lp64d)) +$(eval $(call compile_template,hypervisor-svadu,-march=rv64gh -mabi=lp64d)) else $(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32)) |