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| author | Tim Newsome <tim@sifive.com> | 2016-12-07 20:42:31 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-12-07 20:42:31 -0800 |
| commit | b0e409142ae6984ce1f25126c66ee755c5fe3da1 (patch) | |
| tree | 1b857e6543987138ea598754a7493b6a8af23d70 /debug | |
| parent | 6427012c6de3daf4a108cbda17d4ceb6a79a9d91 (diff) | |
| download | riscv-tests-b0e409142ae6984ce1f25126c66ee755c5fe3da1.zip riscv-tests-b0e409142ae6984ce1f25126c66ee755c5fe3da1.tar.gz riscv-tests-b0e409142ae6984ce1f25126c66ee755c5fe3da1.tar.bz2 | |
Use XLEN macro for these sources as well.
All tests pass on spike32 and spike64 again.
Diffstat (limited to 'debug')
| -rwxr-xr-x | debug/programs/entry.S | 2 | ||||
| -rw-r--r-- | debug/programs/mprv.S | 4 | ||||
| -rw-r--r-- | debug/programs/trigger.S | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index a2c7304..a5e745d 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -5,7 +5,7 @@ #define STACK_SIZE 512 -#if __riscv_xlen == 64 +#if XLEN == 64 # define LREG ld # define SREG sd # define REGBYTES 8 diff --git a/debug/programs/mprv.S b/debug/programs/mprv.S index 5e21607..574f32e 100644 --- a/debug/programs/mprv.S +++ b/debug/programs/mprv.S @@ -12,7 +12,7 @@ main: # update mstatus csrr t1, CSR_MSTATUS -#if __riscv_xlen == 32 +#if XLEN == 32 li t0, (MSTATUS_MPRV | (VM_SV32 << 24)) #else li t0, (MSTATUS_MPRV | (VM_SV39 << 24)) @@ -38,7 +38,7 @@ data: .balign 0x1000 page_table: -#if __riscv_xlen == 32 +#if XLEN == 32 .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) #else .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S index 48cd68b..d87b71e 100644 --- a/debug/programs/trigger.S +++ b/debug/programs/trigger.S @@ -1,6 +1,6 @@ #include "../../env/encoding.h" -#if __riscv_xlen == 64 +#if XLEN == 64 # define LREG ld # define SREG sd # define REGBYTES 8 |