Added FreedomE300 Simulator target

5 files changed, 138 insertions, 10 deletions

diff --git a/debug/README.md b/debug/README.md
index 4a90c0c..8424b87 100644
--- a/debug/README.md
+++ b/debug/README.md
@@ -19,11 +19,17 @@ Targets
 
 `./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
 
-32-bit SiFive Core on Arty FPGA board
+32-bit SiFive Core on Supported FPGA boards
 -------------------------------------
 
 `./gdbserver.py --freedom-e300`
 
+32-bit rocket-chip core in Simulation
+-------------------------------------
+
+`./gdbserver.py --freedom-e300-sim`
+
+
 Debug Tips
 ==========
 
diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index f20630e..aa76ceb 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -10,6 +10,7 @@ import time
 import random
 import binascii
 
+
 MSTATUS_UIE = 0x00000001
 MSTATUS_SIE = 0x00000002
 MSTATUS_HIE = 0x00000004
@@ -72,9 +73,9 @@ class SimpleRegisterTest(DeleteServer):
         # For now gdb has to be told what the architecture is when it's not
         # given an ELF file.
         self.gdb.command("set arch riscv:rv%d" % target.xlen)
-
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
-
+       
         # 0x13 is nop
         self.gdb.command("p *((int*) 0x%x)=0x13" % target.ram)
         self.gdb.command("p *((int*) 0x%x)=0x13" % (target.ram + 4))
@@ -112,6 +113,7 @@ class SimpleMemoryTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("set arch riscv:rv%d" % target.xlen)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
 
     def access_test(self, size, data_type):
@@ -169,8 +171,9 @@ class InstantHaltTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("set arch riscv:rv%d" % target.xlen)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
-
+         
     def test_instant_halt(self):
         self.assertEqual(target.reset_vector, self.gdb.p("$pc"))
         # mcycle and minstret have no defined reset value.
@@ -200,6 +203,7 @@ class DebugTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("file %s" % self.binary)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
         self.gdb.load()
         self.gdb.b("_exit")
@@ -353,6 +357,7 @@ class StepTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("file %s" % self.binary)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
         self.gdb.load()
         self.gdb.b("main")
@@ -371,6 +376,7 @@ class RegsTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("file %s" % self.binary)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
         self.gdb.load()
         self.gdb.b("main")
@@ -441,8 +447,9 @@ class DownloadTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("file %s" % self.binary)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
-
+        
     def test_download(self):
         output = self.gdb.load()
         self.gdb.command("b _exit")
@@ -455,6 +462,7 @@ class MprvTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("file %s" % self.binary)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
         self.gdb.load()
 
@@ -472,6 +480,7 @@ class PrivTest(DeleteServer):
         self.server = target.server()
         self.gdb = gdb()
         self.gdb.command("file %s" % self.binary)
+        self.gdb.command("set remotetimeout %d" % target.timeout)
         self.gdb.command("target extended-remote localhost:%d" % self.server.port)
         self.gdb.load()
 
@@ -520,7 +529,8 @@ class PrivTest(DeleteServer):
 
 class Target(object):
     directory = None
-
+    timeout = 2
+    
     def server(self):
         raise NotImplementedError
 
@@ -574,23 +584,42 @@ class FreedomE300Target(Target):
         return testlib.Openocd(cmd=parsed.cmd,
                 config="targets/%s/openocd.cfg" % self.name)
 
+class FreedomE300SimTarget(Target):
+    name = "freedom-e300-sim"
+    xlen = 32
+    timeout = 240
+    ram = 0x80000000
+    ram_size = 256 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+       
+    def server(self):
+        sim = testlib.VcsSim(simv=parsed.run)
+        x = testlib.Openocd(cmd=parsed.cmd,
+                            config="targets/%s/openocd.cfg" % self.name,
+                            keepAlive = sim)
+        time.sleep(20)
+        return x
+    
 targets = [
         Spike32Target,
         Spike64Target,
-        FreedomE300Target
+        FreedomE300Target,
+        FreedomE300SimTarget
         ]
 
 def main():
     parser = argparse.ArgumentParser(
             epilog="""
             Example command line from the real world:
-            Run all RegsTest cases against a MicroSemi m2gl_m2s board, with custom openocd command:
-            ./gdbserver.py --m2gl_m2s --cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" -- -vf RegsTest
+            Run all RegsTest cases against a physical FPGA, with custom openocd command:
+            ./gdbserver.py --freedom-e-300 --cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" -- -vf RegsTest
             """)
     group = parser.add_mutually_exclusive_group(required=True)
     for t in targets:
         group.add_argument("--%s" % t.name, action="store_const", const=t,
                 dest="target")
+    parser.add_argument("--run",
+                        help="The command to use to start the actual target (e.g. simulation)")
     parser.add_argument("--cmd",
             help="The command to use to start the debug server.")
     parser.add_argument("--gdb",
diff --git a/debug/targets/freedom-e300-sim/link.lds b/debug/targets/freedom-e300-sim/link.lds
new file mode 100755
index 0000000..1dbb99c
--- /dev/null
+++ b/debug/targets/freedom-e300-sim/link.lds
@@ -0,0 +1,34 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    _gp = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg
new file mode 100644
index 0000000..767d229
--- /dev/null
+++ b/debug/targets/freedom-e300-sim/openocd.cfg
@@ -0,0 +1,19 @@
+adapter_khz     10000
+
+source [find interface/jtag_vpi.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+#reset_config trst_and_srst separate
+# Stupid long so I can see the LEDs
+#adapter_nsrst_delay 2000
+#jtag_ntrst_delay 1000
+#
+init
+#reset
+
+halt
diff --git a/debug/testlib.py b/debug/testlib.py
index b3f8f66..d6044f5 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -5,6 +5,7 @@ import subprocess
 import tempfile
 import testlib
 import unittest
+import time
 
 # Note that gdb comes with its own testsuite. I was unable to figure out how to
 # run that testsuite against the spike simulator.
@@ -76,8 +77,47 @@ class Spike(object):
     def wait(self, *args, **kwargs):
         return self.process.wait(*args, **kwargs)
 
+class VcsSim(object):
+    def __init__(self, simv=None, debug=False):
+        if simv:
+            cmd = shlex.split(simv)
+        else:
+            cmd =  ["simv"]
+        cmd += ["+jtag_vpi_enable"]
+        if debug:
+            cmd[0] = cmd[0] + "-debug"
+            cmd += ["+vcdplusfile=output/gdbserver.vpd"]
+        logfile = open("simv.log", "w")
+        logfile.write("+ %s\n" % " ".join(cmd))
+        logfile.flush()
+        listenfile = open("simv.log", "r")
+        listenfile.seek(0,2)
+        self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE, stdout=logfile,
+                                        stderr=logfile)
+        done = False
+        while (not done):
+            line = listenfile.readline()
+            if (not line):
+                time.sleep(1)
+            if ("Listening on port 5555" in line):
+                done = True
+            
+    def __del__(self):
+        print "DELETE called for VcsSim"
+        try:
+            self.process.kill()
+            self.process.wait()
+        except OSError:
+            pass
+
+        
 class Openocd(object):
-    def __init__(self, cmd=None, config=None, debug=False):
+    def __init__(self, cmd=None, config=None, debug=False, keepAlive=None):
+
+        # keep handles to other processes -- don't let them be
+        # garbage collected yet.
+
+        self.keepAlive = keepAlive
         if cmd:
             cmd = shlex.split(cmd)
         else: