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| author | Tim Newsome <tim@sifive.com> | 2016-12-07 20:03:36 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-12-07 20:03:36 -0800 |
| commit | 6427012c6de3daf4a108cbda17d4ceb6a79a9d91 (patch) | |
| tree | f2dc501d908d0deef3e8fd5c8cf89eb579c89285 /debug | |
| parent | 0949ce92a07ee76ad15907b0021addd8a9b053e5 (diff) | |
| download | riscv-tests-6427012c6de3daf4a108cbda17d4ceb6a79a9d91.zip riscv-tests-6427012c6de3daf4a108cbda17d4ceb6a79a9d91.tar.gz riscv-tests-6427012c6de3daf4a108cbda17d4ceb6a79a9d91.tar.bz2 | |
Use our own XLEN macro.
Relying on something that the compiler automatically sets is apparently
not reliable.
Diffstat (limited to 'debug')
| -rw-r--r-- | debug/programs/regs.S | 2 | ||||
| -rw-r--r-- | debug/targets.py | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/debug/programs/regs.S b/debug/programs/regs.S index 5c4f462..200184d 100644 --- a/debug/programs/regs.S +++ b/debug/programs/regs.S @@ -1,4 +1,4 @@ -#if __riscv_xlen == 64 +#if XLEN == 64 # define LREG ld # define SREG sd # define REGBYTES 8 diff --git a/debug/targets.py b/debug/targets.py index d1ba964..8c725c4 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -49,6 +49,7 @@ class Target(object): "-T", "targets/%s/link.lds" % (self.directory or self.name), "-nostartfiles", "-mcmodel=medany", + "-DXLEN=%d" % self.xlen, "-o", binary_name), xlen=self.xlen) return binary_name |