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| author | Tim Newsome <tim@sifive.com> | 2016-12-07 19:52:00 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-12-07 19:52:00 -0800 |
| commit | 0949ce92a07ee76ad15907b0021addd8a9b053e5 (patch) | |
| tree | 953c12a0daf699b5903516e8a9f9f3a348eed4c4 /debug | |
| parent | 2a9e7a9fb66dddbb40e59887450fba4a1ca6c14b (diff) | |
| download | riscv-tests-0949ce92a07ee76ad15907b0021addd8a9b053e5.zip riscv-tests-0949ce92a07ee76ad15907b0021addd8a9b053e5.tar.gz riscv-tests-0949ce92a07ee76ad15907b0021addd8a9b053e5.tar.bz2 | |
We *do* need the FPU to compile 64-bit code.
Diffstat (limited to 'debug')
| -rw-r--r-- | debug/targets.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index 538caaf..d1ba964 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -64,6 +64,7 @@ class SpikeTarget(Target): class Spike64Target(SpikeTarget): name = "spike64" xlen = 64 + use_fpu = True def server(self): return testlib.Spike(self.cmd, halted=True) |