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authorTim Newsome <tim@sifive.com>2017-08-10 11:43:49 -0700
committerTim Newsome <tim@sifive.com>2017-08-10 11:43:49 -0700
commitd44ebb21c0131c661575539771a1d97fc9afa4c1 (patch)
tree2c0b0ee2210e50b061a9e06f1fc8383fb7e33b79 /debug
parent130702297a010b4a2e7452bb48f0da88c0b30aa9 (diff)
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Give these sim targets a chance of passing.
Also make sure vsim.log makes it into the generated log file.
Diffstat (limited to 'debug')
-rw-r--r--debug/targets/SiFive/Freedom/E300Sim.py3
-rw-r--r--debug/targets/SiFive/Freedom/U500Sim.py7
-rw-r--r--debug/testlib.py6
3 files changed, 11 insertions, 5 deletions
diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py
index e98c5b9..91be2e8 100644
--- a/debug/targets/SiFive/Freedom/E300Sim.py
+++ b/debug/targets/SiFive/Freedom/E300Sim.py
@@ -1,4 +1,5 @@
import targets
+import testlib
class E300Sim(targets.Target):
xlen = 32
@@ -9,5 +10,5 @@ class E300Sim(targets.Target):
openocd_config_path = "Freedom.cfg"
link_script_path = "Freedom.lds"
- def target(self):
+ def create(self):
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py
index 7648960..62bc827 100644
--- a/debug/targets/SiFive/Freedom/U500Sim.py
+++ b/debug/targets/SiFive/Freedom/U500Sim.py
@@ -1,4 +1,7 @@
-class U500Sim(Target):
+import targets
+import testlib
+
+class U500Sim(targets.Target):
xlen = 64
timeout_sec = 6000
ram = 0x80000000
@@ -7,5 +10,5 @@ class U500Sim(Target):
openocd_config_path = "Freedom.cfg"
link_script_path = "Freedom.lds"
- def target(self):
+ def create(self):
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/debug/testlib.py b/debug/testlib.py
index debe368..597c69b 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -116,6 +116,8 @@ class Spike(object):
return self.process.wait(*args, **kwargs)
class VcsSim(object):
+ logname = "simv.log"
+
def __init__(self, sim_cmd=None, debug=False):
if sim_cmd:
cmd = shlex.split(sim_cmd)
@@ -125,10 +127,10 @@ class VcsSim(object):
if debug:
cmd[0] = cmd[0] + "-debug"
cmd += ["+vcdplusfile=output/gdbserver.vpd"]
- logfile = open("simv.log", "w")
+ logfile = open(self.logname, "w")
logfile.write("+ %s\n" % " ".join(cmd))
logfile.flush()
- listenfile = open("simv.log", "r")
+ listenfile = open(self.logname, "r")
listenfile.seek(0, 2)
self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
stdout=logfile, stderr=logfile)