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author | Tim Newsome <tim@sifive.com> | 2023-10-03 09:08:00 -0700 |
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committer | GitHub <noreply@github.com> | 2023-10-03 09:08:00 -0700 |
commit | 9905a434c9da6588763b31dd01d263144e0db0ed (patch) | |
tree | 476606a51aa113052c58b17c96702244c6c7d593 /debug/testlib.py | |
parent | 39fc8b09553a563865c274d891643c7246db6783 (diff) | |
parent | 903ec8243fc8af856ac549fcbfbd78835f2c3556 (diff) | |
download | riscv-tests-9905a434c9da6588763b31dd01d263144e0db0ed.zip riscv-tests-9905a434c9da6588763b31dd01d263144e0db0ed.tar.gz riscv-tests-9905a434c9da6588763b31dd01d263144e0db0ed.tar.bz2 |
Merge pull request #508 from riscv-software-src/set_available
debug: Add Openocd.set_available()
Diffstat (limited to 'debug/testlib.py')
-rw-r--r-- | debug/testlib.py | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/debug/testlib.py b/debug/testlib.py index baa7783..5303f84 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -497,6 +497,30 @@ class Openocd: if time.time() - start > self.timeout: raise TestLibError("Timed out waiting for targets to run.") + def set_available(self, harts): + """Set the given harts to available, and any others to be unavailable. + This uses a custom DMI register (0x1f) that is only implemented in + spike.""" + available_mask = 0 + for hart in harts: + available_mask |= 1 << hart.id + self.command(f"riscv dmi_write 0x1f 0x{available_mask:x}") + + # Wait until it happened. + start = time.time() + while True: + currently_available = set() + currently_unavailable = set() + for i, target in enumerate(self.targets()): + if target["State"] == "unavailable": + currently_unavailable.add(i) + else: + currently_available.add(i) + if currently_available == set(hart.id for hart in harts): + return + if time.time() - start > self.timeout: + raise TestLibError("Timed out waiting for hart availability.") + class OpenocdCli: def __init__(self, port=4444): self.child = pexpect.spawn( |