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authorTim Newsome <tim@sifive.com>2018-02-19 13:31:40 -0800
committerTim Newsome <tim@sifive.com>2018-03-01 15:19:25 -0800
commitfc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5 (patch)
tree14038bee96c5aa4351465fd54c44f0e2ebe069ba /debug/testlib.py
parent208298c733a0e5ba9e4f7f892123745bdc7156c1 (diff)
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Test debugging with/without a program buffer
Diffstat (limited to 'debug/testlib.py')
-rw-r--r--debug/testlib.py7
1 files changed, 6 insertions, 1 deletions
diff --git a/debug/testlib.py b/debug/testlib.py
index 3aaa542..5c40a5d 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -57,11 +57,12 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin
class Spike(object):
def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
- isa=None):
+ isa=None, progbufsize=None):
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
self.isa = isa
+ self.progbufsize = progbufsize
if target.harts:
harts = target.harts
@@ -118,6 +119,10 @@ class Spike(object):
cmd += ["--isa", isa]
+ if not self.progbufsize is None:
+ cmd += ["--progsize", str(self.progbufsize)]
+ cmd += ["--debug-sba", "32"]
+
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"
assert len(set(t.ram_size for t in harts)) == 1, \