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authorTim Newsome <tim@sifive.com>2020-08-06 08:50:43 -0700
committerGitHub <noreply@github.com>2020-08-06 08:50:43 -0700
commitf68760e7e0295a03ccf3147571f4254cc352e4fc (patch)
tree2717e7a300d974813ab06a31622bafab530379a8 /debug/targets
parent3261a3107b7b921dfcc577282e715e2e2fba60ea (diff)
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Add enable_rtos_riscv (#288)
This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287.
Diffstat (limited to 'debug/targets')
-rw-r--r--debug/targets/RISC-V/spike-rtos.cfg2
1 files changed, 2 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 7cd1c3f..395a9f8 100644
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -8,6 +8,8 @@ remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+enable_rtos_riscv
+
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv