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author | Tim Newsome <tim@sifive.com> | 2021-05-07 11:49:42 -0700 |
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committer | GitHub <noreply@github.com> | 2021-05-07 11:49:42 -0700 |
commit | c9f43c1652c1d8abf85f3466f41ffd5ec4d911d6 (patch) | |
tree | 21306f7c8d15ad937e2e234d564e81a0e43efa86 /debug/targets | |
parent | 1b05661baa79f03830f5ddefa999dc7aaf7b1ce1 (diff) | |
download | riscv-tests-c9f43c1652c1d8abf85f3466f41ffd5ec4d911d6.zip riscv-tests-c9f43c1652c1d8abf85f3466f41ffd5ec4d911d6.tar.gz riscv-tests-c9f43c1652c1d8abf85f3466f41ffd5ec4d911d6.tar.bz2 |
Test daisy chained homogeneous spike instances. (#334)
* Test debugging multiple spikes in a daisy chain.
* Hugely speed up rbb_daisychain.
Now 2 dual-hart spikes are less than 4x slower than a single dual-hart
spike.
* WIP
* Test daisy chained homogeneous spike instances.
For OpenOCD, this means we're checking that we can talk to multiple
TAPs. Next up is heterogeneous testing.
* Enable Sv48Test.
Didn't mean to disable it with this commit.
* Test authentication again.
Another change I hadn't meant to push...
Diffstat (limited to 'debug/targets')
-rw-r--r-- | debug/targets/RISC-V/spike-multi.cfg | 46 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike-multi.py | 39 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike32.py | 3 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike64.py | 3 |
4 files changed, 89 insertions, 2 deletions
diff --git a/debug/targets/RISC-V/spike-multi.cfg b/debug/targets/RISC-V/spike-multi.cfg new file mode 100644 index 0000000..ef6dfc6 --- /dev/null +++ b/debug/targets/RISC-V/spike-multi.cfg @@ -0,0 +1,46 @@ +# Connect to a mult-icore RISC-V target, exposing each hart as a thread. +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host $::env(REMOTE_BITBANG_HOST) +remote_bitbang_port $::env(REMOTE_BITBANG_PORT) + +jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913 + +target create riscv.0.cpu0 riscv -chain-position riscv.0.cpu -coreid 0 +target create riscv.0.cpu1 riscv -chain-position riscv.0.cpu -coreid 1 +target create riscv.1.cpu0 riscv -chain-position riscv.1.cpu -coreid 0 +target create riscv.1.cpu1 riscv -chain-position riscv.1.cpu -coreid 1 + +riscv.0.cpu0 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1 +riscv.0.cpu1 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1 +riscv.1.cpu0 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1 +riscv.1.cpu1 configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1 + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +foreach t [target names] { + targets $t + riscv expose_csrs 2288 + riscv expose_custom 1,12345-12348 +} + +init + +targets riscv.0.cpu0 +set challenge [riscv authdata_read] +riscv authdata_write [expr $challenge + 1] + +targets riscv.1.cpu0 +set challenge [riscv authdata_read] +riscv authdata_write [expr $challenge + 1] + +foreach t [target names] { + targets $t + halt + arm semihosting enable +} diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py new file mode 100644 index 0000000..9e85a35 --- /dev/null +++ b/debug/targets/RISC-V/spike-multi.py @@ -0,0 +1,39 @@ +import targets +import testlib + +import spike32 # pylint: disable=import-error +#import spike64 # pylint: disable=import-error + +class multispike(targets.Target): + harts = [ + spike32.spike32_hart(misa=0x4034112d, system=0), + spike32.spike32_hart(misa=0x4034112d, system=0), + spike32.spike32_hart(misa=0x4034112d, system=1), + spike32.spike32_hart(misa=0x4034112d, system=1)] + #spike64.spike64_hart(misa=0x8000000000341129), + #spike64.spike64_hart(misa=0x8000000000341129)] + openocd_config_path = "spike-multi.cfg" + # Increased timeout because we use abstract_rti to artificially slow things + # down. + timeout_sec = 30 + implements_custom_test = True + support_hasel = False + support_memory_sampling = False # Needs SBA + + def create(self): + # TODO: It would be nice to test with slen=128, but spike currently + # requires vlen==slen. + return testlib.MultiSpike( + [ +# testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30, +# support_hasel=False, support_abstract_csr=False, +# vlen=512, elen=64, slen=512, harts=self.harts[:2]), + testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4, + support_abstract_csr=True, support_haltgroups=False, + # elen must be at least 64 because D is supported. + elen=64, harts=self.harts[2:]), + testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4, + support_abstract_csr=True, support_haltgroups=False, + # elen must be at least 64 because D is supported. + elen=64, harts=self.harts[2:]) + ]) diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 381aea7..6256574 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -10,7 +10,8 @@ class spike32_hart(targets.Hart): reset_vectors = [0x1000] link_script_path = "spike32.lds" - def __init__(self, misa): + def __init__(self, misa, system=0): + super().__init__(system=system) self.misa = misa class spike32(targets.Target): diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index c4c66c8..4313968 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -10,7 +10,8 @@ class spike64_hart(targets.Hart): reset_vectors = [0x1000] link_script_path = "spike64.lds" - def __init__(self, misa=0x8000000000141125): + def __init__(self, misa=0x8000000000141125, system=0): + super().__init__(system=system) self.misa = misa class spike64(targets.Target): |