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| author | Tim Newsome <tim@sifive.com> | 2018-02-19 13:31:40 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-02-28 12:37:40 -0800 |
| commit | 400ad944db31fe736c166967567cc8a63d300e6c (patch) | |
| tree | c21a01a4c99b8f11f5f7e384496828d85e14e16c /debug/targets/RISC-V/spike64.py | |
| parent | ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241 (diff) | |
| download | riscv-tests-no_progbuf.zip riscv-tests-no_progbuf.tar.gz riscv-tests-no_progbuf.tar.bz2 | |
Test debugging with/without a program bufferno_progbuf
Diffstat (limited to 'debug/targets/RISC-V/spike64.py')
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 2aa1dd0..d5802b5 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -16,4 +16,4 @@ class spike64(targets.Target): def create(self): # 32-bit FPRs only - return testlib.Spike(self, isa="RV64IMAFC") + return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0) |