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| author | Tim Newsome <tim@sifive.com> | 2022-06-02 11:08:30 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-06-06 09:05:26 -0700 |
| commit | 62a1beccc7a65f982af4a49be5300617b694f5b2 (patch) | |
| tree | 14f0db751a901df73290c7e6ccf523c01cdb6d52 /debug/pylint.rc | |
| parent | 30e5368a7bb341dcff001ec8a56fcfd0ae8fda2f (diff) | |
| download | riscv-tests-62a1beccc7a65f982af4a49be5300617b694f5b2.zip riscv-tests-62a1beccc7a65f982af4a49be5300617b694f5b2.tar.gz riscv-tests-62a1beccc7a65f982af4a49be5300617b694f5b2.tar.bz2 | |
Add unaligned test cases for lw
The test passes if either the target register contains the correct
value, or the target raises a misaligned load exception.
Diffstat (limited to 'debug/pylint.rc')
0 files changed, 0 insertions, 0 deletions