aboutsummaryrefslogtreecommitdiff
path: root/debug/programs/step.S
diff options
context:
space:
mode:
authorTim Newsome <tim@sifive.com>2016-06-21 19:20:27 -0700
committerTim Newsome <tim@sifive.com>2016-07-18 18:51:54 -0700
commit7c9510e7a7e224ee3d51ebe736a58f81017a71a0 (patch)
tree9a1baa1eed4c79b5717e368c6ac0d19c6fb30d23 /debug/programs/step.S
parent78991b2a1d8e48b7280101d3a69128ff24dc4305 (diff)
downloadriscv-tests-7c9510e7a7e224ee3d51ebe736a58f81017a71a0.zip
riscv-tests-7c9510e7a7e224ee3d51ebe736a58f81017a71a0.tar.gz
riscv-tests-7c9510e7a7e224ee3d51ebe736a58f81017a71a0.tar.bz2
Test step over invalid instruction.
Diffstat (limited to 'debug/programs/step.S')
-rw-r--r--debug/programs/step.S21
1 files changed, 14 insertions, 7 deletions
diff --git a/debug/programs/step.S b/debug/programs/step.S
index 49f82d6..6601548 100644
--- a/debug/programs/step.S
+++ b/debug/programs/step.S
@@ -3,15 +3,22 @@
.global main
main:
- li t0, 5 // 0
- beq zero, zero, one // 0x4
- nop // 0x8
+ la t0, trap_entry // 0, 4
+ csrw mtvec, t0 // 0x8
+
+ li t0, 5 // 0xc
+ beq zero, zero, one // 0x10
+ nop // 0x14
one:
- beq zero, t0, one // 0xc
- jal two // 0x10
+ beq zero, t0, one // 0x18
+ jal two // 0x1c
three:
- j three // 0x14
+ .word 0 // 0x20
+ nop // 0x24
two:
- ret // 0x18
+ ret // 0x28
+
+trap_entry:
+ j trap_entry // 0x2c