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author | Tim Newsome <tim@sifive.com> | 2016-12-27 11:34:50 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2016-12-27 11:34:50 -0800 |
commit | 4ec77dde62f8c14df9403abf7b10a2455ea72125 (patch) | |
tree | ce54ad127f65f392c149d66d1caf84c677d8daec /debug/programs/step.S | |
parent | b986817eebe9bd810be371dc84ee94e8f654de42 (diff) | |
download | riscv-tests-4ec77dde62f8c14df9403abf7b10a2455ea72125.zip riscv-tests-4ec77dde62f8c14df9403abf7b10a2455ea72125.tar.gz riscv-tests-4ec77dde62f8c14df9403abf7b10a2455ea72125.tar.bz2 |
Use compressed code if the target supports it.
The main change was to read misa before running any other test. If misa
indicates C is supported, then use compressed code. This required
changing some tests, mostly to ensure correct alignment. The single
step test also needs to know the correct addresses to step through in
compressed code.
Only print at most 1000 lines from each log file.
Diffstat (limited to 'debug/programs/step.S')
-rw-r--r-- | debug/programs/step.S | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/debug/programs/step.S b/debug/programs/step.S index 6601548..3e7b42e 100644 --- a/debug/programs/step.S +++ b/debug/programs/step.S @@ -11,14 +11,18 @@ main: nop // 0x14 one: beq zero, t0, one // 0x18 - jal two // 0x1c + // Use t0 instead of ra to force a 32-bit opcode in C mode. Otherwise + // 32-bit and 64-bit binaries end up with different instructions (I + // didn't pursue this). + jal t0, two // 0x1c three: .word 0 // 0x20 nop // 0x24 two: - ret // 0x28 + jr t0 // 0x28 + .align 2 trap_entry: j trap_entry // 0x2c |