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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-04-21 14:58:47 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-04-21 14:58:47 -0700 |
| commit | e9c88267da591b8b60d3b2e7bd790b6a01ab6ec5 (patch) | |
| tree | 3bebfa213978101ce1bf1beb446a0b7c077752d9 | |
| parent | bcf83a88846468dcb294e2646270f433d967cf26 (diff) | |
| download | riscv-tests-e9c88267da591b8b60d3b2e7bd790b6a01ab6ec5.zip riscv-tests-e9c88267da591b8b60d3b2e7bd790b6a01ab6ec5.tar.gz riscv-tests-e9c88267da591b8b60d3b2e7bd790b6a01ab6ec5.tar.bz2 | |
Don't rely on reset values of MSTATUS_UA/SA
| -rw-r--r-- | benchmarks/common/crt.S | 19 | ||||
| -rw-r--r-- | benchmarks/common/syscalls.c | 2 |
2 files changed, 18 insertions, 3 deletions
diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index 19ff3b2..0c99c4a 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -67,8 +67,23 @@ _start: li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator -#ifndef __riscv64 - li t0, MSTATUS_UA; csrc mstatus, t0 # disable RV64 for user mode + li t0, ((MSTATUS64_UA & ~(MSTATUS64_UA << 1)) * UA_RV64) >> 31 + sll t0, t0, 31 + li t1, ((MSTATUS64_SA & ~(MSTATUS64_SA << 1)) * UA_RV64) >> 31 + sll t1, t1, 31 +#ifdef __riscv64 + # make sure processor supports RV64 if this was compiled for RV64 + bnez t0, 1f + li a0, 1234 + j tohost_exit +1: + # enable RV64 for user and supervisor + csrs mstatus, t0 + csrs mstatus, t1 +#else + # disable RV64 for user and supervisor + csrc mstatus, t0 + csrc mstatus, t1 #endif csrr t0, mstatus diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c index 4c494f1..3c08bc2 100644 --- a/benchmarks/common/syscalls.c +++ b/benchmarks/common/syscalls.c @@ -60,7 +60,7 @@ static int handle_stats(int enable) return 0; } -static void tohost_exit(int code) +void tohost_exit(long code) { write_csr(tohost, (code << 1) | 1); while (1); |