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| author | Tim Newsome <tim@sifive.com> | 2022-05-25 14:25:37 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-05-25 14:25:37 -0700 |
| commit | 57ce728f7db0c2b05d429471f94becf6302735c0 (patch) | |
| tree | 1006aa7441440dfbf5a617b219cf4a95b3f6b2ee | |
| parent | fd6e7ed1707b3449f9673fa6b3bc1e422af4669b (diff) | |
| download | riscv-tests-57ce728f7db0c2b05d429471f94becf6302735c0.zip riscv-tests-57ce728f7db0c2b05d429471f94becf6302735c0.tar.gz riscv-tests-57ce728f7db0c2b05d429471f94becf6302735c0.tar.bz2 | |
Address trigger has higher priority than alignment
Used this test to confirm that
https://github.com/riscv-software-src/riscv-isa-sim/pull/1013 works
right.
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 252a696..4cf51a4 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -98,6 +98,51 @@ RVTEST_CODE_BEGIN bnez a2, fail 2: + # Test that address breakpoints have higher priority than unaligned loads. + li TESTNUM, 12 + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD | MCONTROL_STORE + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + bne a0, a1, 2f + la a2, data1 + 1 + la a3, data3 + csrw tdata2, a2 + + # Slow path because CSR was *just* written. (This is spike-specific.) + lw a2, (a2) + beqz a2, fail + + # Normal aligned load, so that the next time we'll hit the fast path. + li TESTNUM, 13 + lw a0, (a3) + + # Fast path + li TESTNUM, 14 + lw a2, (a2) + beqz a2, fail + + # Test that address breakpoints have higher priority than unaligned stores. + li TESTNUM, 16 + + la a2, data1 + 1 + csrw tdata2, a2 + + # Slow path because CSR was *just* written. (This is spike-specific.) + sw x0, (a2) + beqz a2, fail + + # Normal aligned store, so that the next time we'll hit the fast path. + li TESTNUM, 17 + sw x0, (a3) + + # Fast path + li TESTNUM, 18 + sw x0, (a2) + beqz a2, fail + + +2: TEST_PASSFAIL .align 2 @@ -125,5 +170,6 @@ RVTEST_DATA_BEGIN data1: .word 0 data2: .word 0 +data3: .word 0 RVTEST_DATA_END |